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layout

  • Database Error while Generating Artwork

    I'll start from the beginning: - I was working in a design and OrCAD PCB Designer crashed saying "Orcad has encountered an error and needs to close." or something to that effect. Then I clicked ok and the program shut down. - I opened it back up and continued to work. Everything seemed...
    Posted to PCB Design (Forum) by melview1 on Fri, May 28 2010
  • How to create templates for vdd/vss nets in Virtuoso

    I am working on the layout of a full custom digital design in Virtuoso. I have now fixed my pitch for the vdd and vss nets. Can anyone tell me as to how i can create templates of some sort of a ruler/guide for these nets which can help me to see where my vdd vss nets/tracks would lie in the layout .It...
    Posted to Custom IC Design (Forum) by akbhide on Mon, May 17 2010
  • Re: Short between IO filler blockage and IO pad pin

    To avoid shorts you have at least 2 ways: 1. If blockage represents actual wire in the filler (not pad ring) then shorts are valid and you need to resize pad pin in IO cell to meet spacing (maybe you need to consider width-depended spacing rules). 2. If blockage comes from pad ring wires in the fille...
    Posted to Digital Implementation (Forum) by mikhail on Wed, Apr 28 2010
  • Filler Cells and Substrate Contacts in Virtuoso GXL

    Hi, I am using the student version of cadence tools at my Univ to auto place and route a custom design, using standard-cells. I am using the Custom IC tools suggested, i.e Schematic XL and Virtuoso GXL. I design the schematic of the architecture, first, then using the connectivity driven option, i generate...
    Posted to Custom IC Design (Forum) by nbtarun on Wed, Apr 7 2010
  • VIRTUOSO GXL Auto-Place & Route problems

    Hi, I am using the student version of cadence tools at my Univ to auto place and route a custom design, using standard-cells. I am using the Custom IC tools suggested, i.e Schematic XL and Virtuoso GXL. I design the schematic of the architecture, first, then using the connectivity driven option, i generate...
    Posted to Custom IC Design (Forum) by nbtarun on Sat, Apr 3 2010
  • What's Good About Support Service And Design Bureau Providers? AcAe Can Help!

    I usually discuss our SPB solution technical capabilities in my weekly blogs, but decided to chat about this week's press announcement - " Cadence Teams with AcAe to Accelerate Customer Transitions to Allegro PCB Products " - and ask what works the best for you when you've engaged with...
    Posted to PCB Design (Weblog) by Jerry GenPart on Wed, Mar 31 2010
  • Antenna Error in Calibre DRC but Passed antenna check in Encounter

    Dear Experts, I am using encounter to do my place and route after having obtain the macro lef from the abstract generator, everything's going fine until i stream out my gds2 file and check the DRC using Calibre in virtuoso, where i am getting hundreds of antenna error out of the antenna check. I...
    Posted to Digital Implementation (Forum) by mingfatty on Tue, Mar 16 2010
  • Error when loading LEF file

    i'm new in using Encounter i've problem when loading LEF file i got the following error encounter 1> Reading config file - /root/Desktop/tech/Default.conf Loading Lef file /root/Desktop/tech/antenna_9.lef... Initializing default via types and wire widths ... Loading Lef file /root/Desktop...
    Posted to Digital Implementation (Forum) by eng samy on Wed, Feb 24 2010
  • Delete, out of date shape

    Hello, new user, learning, currently running OrCAD PCB Designer 16.2. I am trying to create the artwork of a test PCB, message is Dynamic shapes need updating. Goto View Status, Out of date shapes 1/22. Dynamic shapes state: Dynamic shapes out of date: 1 out of 22 Current fill mode : SMOOTH Layer = TOP...
    Posted to PCB Design (Forum) by Rolf2U on Wed, Feb 17 2010
  • vdd not sensed in post-layout simulation

    Hi, I tried to do post layout simulation with extracted, symbolized inverter, however, I got the message during simualtion: Notice from spectre during topology check. Only one connection to node 'vdd!' I plot the output and confirmed that vdd is not applied to the internal transistors of the...
    Posted to Custom IC Design (Forum) by Malolo on Tue, Jan 12 2010
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