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layout

  • LIBRARY REVISION VISIBILITY

    We currently distribute our global library over a network folder using hard coded Enviromental Veriables. The problem is that we have no way of knowing when the library was last updated. This can cause users to be un-aware of recent library updates or if they are using old revisions of the library (due...
    Posted to PCB Design (Forum) by Jonah Stephenson on Thu, Aug 19 2010
  • Putting object on grid

    In order to put a path, an object or a guard ring on a current drawing grid, is it possible to do by skill through a bindkey? Where could I find such a skill code or starting code to do this operation? Regards,
    Posted to Custom IC Design (Forum) by frogconsultant on Fri, Aug 6 2010
  • What's Good About Allegro GRE Bundle Editing? SPB16.3 Has Many New Enhancements!

    The Allegro Global Route Environment (GRE) has expanded its capabilities in the area of bundled editing in the SPB16.3 release. It’s now easier to copy, move, and split bundles. Copy Flow lets you copy the flow path from one bundle to another. Its primary goal is to allow faster creation of the...
    Posted to PCB Design (Weblog) by Jerry GenPart on Wed, Jul 28 2010
  • Antenna Trace Relief

    Using Allegro OrCAD PCB Designer v16.3.S009 I have a 2.4GHz impedance controlled antenna trace that has a ground pour around it. I would like to pull back the ground pour at least 30 mils from this antenna trace. Is there a property or something in the net or trace that I can set such that it will automatically...
    Posted to PCB Design (Forum) by melview1 on Thu, Jul 22 2010
  • Cadence 14.0 : DRC error Line to SMD Pin Spacing

    Hello, I route a board on Cadence 14.0 and have an unknown problem. Each time I try to connect 2 pins of a same net, I have 2 DRC errors : Line to SMD Pin Spacing. More over, when I connect these 2 pins, it is not automaticaly directed to the center of the second pin. Is thre anyone who can help me ...
    Posted to PCB Design (Forum) by romaric on Wed, Jul 7 2010
  • What's Good About Vias And The Allegro Router? SPB16.3 Has A Few New Enhancements!

    A few new enhancements specific to vias in the SPB16.3 release of Allegro PCB Editor have been introduced. The are called use via region and stacked via support . Use Via Region Many times you need to restrict usage of specific vias in a region. Allegro PCB Router has been enhanced to allow via usage...
    Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Jun 22 2010
  • Cadence 5: Change path width with bindkey

    Without the possibility to change the default width to the correct value in the PDK, I am trying to develop a bindkey in cadence 5.1.41 which will do the trick. hiSetBindkey("Layout" "<Key>F11" "leHiEditProp() width->value=130") After selection of the path, I am...
    Posted to Custom IC Design (Forum) by frogconsultant on Tue, Jun 22 2010
  • Database Error while Generating Artwork

    I'll start from the beginning: - I was working in a design and OrCAD PCB Designer crashed saying "Orcad has encountered an error and needs to close." or something to that effect. Then I clicked ok and the program shut down. - I opened it back up and continued to work. Everything seemed...
    Posted to PCB Design (Forum) by melview1 on Fri, May 28 2010
  • How to create templates for vdd/vss nets in Virtuoso

    I am working on the layout of a full custom digital design in Virtuoso. I have now fixed my pitch for the vdd and vss nets. Can anyone tell me as to how i can create templates of some sort of a ruler/guide for these nets which can help me to see where my vdd vss nets/tracks would lie in the layout .It...
    Posted to Custom IC Design (Forum) by akbhide on Mon, May 17 2010
  • Re: Short between IO filler blockage and IO pad pin

    To avoid shorts you have at least 2 ways: 1. If blockage represents actual wire in the filler (not pad ring) then shorts are valid and you need to resize pad pin in IO cell to meet spacing (maybe you need to consider width-depended spacing rules). 2. If blockage comes from pad ring wires in the fille...
    Posted to Digital Implementation (Forum) by mikhail on Wed, Apr 28 2010
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