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layers

  • How to generate a list of display layers?

    Hi, I am using cadence virtuoso version IC6.1.5-64b.500.17. I would want to generate a list of layers that is already displaying in my Layout editor window. I already know there is a function call leLSWShowLayers(), but I am not using LSW. I am using layer palette. And I can't bring LSW up using...
    Posted to Custom IC SKILL (Forum) by KokoLiu on Fri, Aug 22 2014
  • CDL extraction

    hi, We have the skill to extract multiple cells from the celllist from the shell. We need to export its cdl from the corresponding schematics. Is there any way to put this extraction on queue.We get only first cell of the cell list is exported. Before the previous cell is extracted the cdl export of...
    Posted to Custom IC SKILL (Forum) by Hith on Thu, Jul 4 2013
  • Calculate local density of specified layers

    I'm interested in writing a SKILL code that calculates local density of any layers specified based on bbox given. I'm wondering what is the best way to achieve this. The function will be given a cellview, bbox, and layers to be processed. For example, getLocalDensity(d_cellview, l_bBox, l_layers...
    Posted to Custom IC SKILL (Forum) by Yaosan Yeo on Thu, Nov 15 2012
  • package symbol on two different layers

    Hello everybody, I work on Cadence 16.3 and I have to create a package symbol on two different layers. On top face, there should be 2 SMD pins and on bottom face, there should be 1 SMD pin. Do you know how to do that ? I do not manage to put a pin on a different layer than bottom. Thanks for all.
    Posted to PCB Design (Forum) by romaric on Mon, May 16 2011
  • procedure for gerber file/plot generation of specific layers - OrCAD PCB editor 16.3

    I have designed a very first circuit board using OrCAD PCb editor 16.3. I wish to generate outputs of the following layers: 1. Top layer, 2. Bottom layer, 3. Silkscreen top layer, 4. Soldermask top layer, 5. Soldermask bottom layer, 6. Drill drawing (location), and 7. Drill drawing (symbol and drill...
    Posted to PCB Design (Forum) by CAT8024 on Wed, Sep 22 2010
  • PCB autorouter(spectraa) not converging

    Hi, I am making my first pcb with a xilinx fpga device(256 pin BGA package).I am simply connecting the all I/O's to 4 standard 40 pin connectors.Are padstacks necessary for PCB routing??.I have drawn the schematic in Capture imported it to Layout_Plus and autorouted it. But after 3 hours of autorouting...
    Posted to PCB Design (Forum) by bennyn1 on Thu, Sep 2 2010
  • Flexi-Rigid contacts / place component on inner layer?

    My current flexi-rigid design: Head section (rigid L1-6), Neck section (flexible L2-5), Body section (rigid L1-6), Tail section (flexible L4-5) with exposed contacts (J1) on L4 for insertion into a ZIF socket. I've created J1 as a component but can't place it on an inner layer i.e. L4. Can components...
    Posted to PCB Design (Forum) by AlanSpectrum on Mon, Aug 16 2010
  • autorouter layer costs

    in allegro 16.0, is there any way to set a higher/lower cost for routing on a particular layer? if so, how? can this be done with a "Do File"? are there any good tutorials out there on Do Files? Thanks
    Posted to PCB Design (Forum) by sharted on Wed, Jun 30 2010
  • routing to gnd/pwr planes

    simple question, but I am not sure how to solve it, since I am new to allegro/pcb editor (16.0). I ran autorouter, and it didn't rout any VCC or GND nets to my VCC or GND layers; they just show up as ratsnest, even though the auto router said it completed 100%. here is an image: http://img94.imageshack...
    Posted to PCB Design (Forum) by sharted on Fri, Jun 18 2010
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