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irun ncsim abv psl sva assertions

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  • Continue after failed PSL assertions

    Hi! I am running a mixed-language simulation with irun. This includes PSL assertions in my VHDL code and SVA assertions in my SystemVerilog/UVM testbench. As the simulation runs in non-interactive mode on a cluster, I do not want the simulation to stop due to failed assertions. It rather should log it...
    Posted to Functional Verification (Forum) by wltr on Wed, Dec 12 2012
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