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  • interconnect check with PSL

    Hi all, I want to check interconnectivity among several IP blocks(in VHDL and Verilog) with PSL vunits. However I have a problem in binding. As I understand, i can bind the vunit to only one entity. But for interconnect check, I need port signals from both entities(IPs) so that I can continiously compare...
    Posted to Functional Verification (Forum) by bjerkely on Wed, Oct 23 2013
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