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Functional Verification Survey -- Why Gate-Level Simulation is Increasing
In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 16 2013
Archived Webinar: New Technology Attacks the Verification Debug Bottleneck
Verification debug hasn't exactly been a hotbed of technology innovation, even though verification teams report that debugging can consume more than 50% of the overall verification effort. A recently archived Cadence webinar reviews common debug challenges and shows how the new Incisive Debug Analyzer...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Nov 29 2012
Keynote: From “Tribulations” to Mixed-Signal Success at Texas Instruments
Texas Instruments has experienced many "tribulations" in mixed analog and digital design, according to Chris Collins, a director at Analog Design Services at TI. But significant progress is underway. At a keynote speech at the recent Mixed-Signal Technology Summit held at Cadence Sept. 20,...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 26 2012
Designer View – Using Metric-Driven Verification for Mixed-Signal IP
Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 29 2012
Webinar: Speeding UVM SystemVerilog Simulation With Software Engineering Techniques
You may be a software engineer and not even know it. If you develop IC verification environments, the way you write and optimize code has a tremendous impact on simulation performance. A recently archived Cadence webinar provided a number of practical tips to help you analyze and optimize Universal Verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 8 2012
User Presentation: Adapting a Specman “e” Simulation Testbench to Emulation
When Intel engineers were asked to verify one of the company's largest Many Integrated Core (MIC) designs, they faced a quandary. On one hand, they wanted the visibility and debug features provided by their Specman e language simulation environment. But they also wanted the much faster speeds provided...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Aug 2 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification
Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 24 2012
DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?
Emulation and FPGA-based prototyping are becoming increasingly necessary for complex systems-on-chip, but where are these hardware-assisted tools going to come from? Should you invest the resources to build and maintain your own, or purchase a commercially available solution? In either case, what do...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 7 2012
Best Practices for Selecting and Using Verification IP (VIP)
In the past few years, commercial verification IP (VIP) has been selected for use in an ever greater percentage of verification environments. While VIP has the capability to save considerable time and engineering resources, there are several decisions you need to make in order to optimize the value received...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 13 2012
Digital and Analog Verification – Round Peg in a Square Hole?
Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Feb 9 2012
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