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industry insights,Virtuoso,Double Patterning

Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

A recent test chip tapeout using the Samsung 14nm FinFET process revealed significant progress in digital implementation at this new process node. Thanks to deep collaboration and extensive R&D investments in libraries, process, and tools, the digital implementation of the test chip was successfully...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 7 2013
Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges

Any discussion about advanced node (below 28nm) that focuses only on digital design is missing an important part of the story. Custom/analog design must be considered too, and that's the subject of a video interview with Tom Beckley, senior vice president of R&D for Custom IC and Simulation at...

Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 5 2012
ARM TechCon: Inside Story of a 14nm FinFET Tapeout

The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 31 2012
TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs

TSMC, the world's largest semiconductor foundry, is thinking big when it comes to next-generation process technology. At the TSMC Open Innovation Platform (OIP) Ecosystem Forum Oct. 16, TSMC described reference flows for 20nm and for multi-die integration, and revealed that ARM and TSMC are working...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 17 2012
Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements

No 20nm IC design "solution" is complete without a custom/analog flow that can develop standard cells and analog/mixed-signal IP blocks. That custom/analog flow requires some changes to keep up with 20nm challenges such as double patterning and layout-dependent effects (LDE). A good overview...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 9 2012

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industry insights,Virtuoso,Double Patterning

Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges

ARM TechCon: Inside Story of a 14nm FinFET Tapeout

TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs

Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements