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Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification
Why is there a need for "best practices" in mixed-signal SoC verification, and what are some of those practices? A presentation at the recent DVCon 2013 conference addressed these questions by showing how Maxim Integrated is bringing digital techniques into mixed-signal verification. Here's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 27 2013
Archived Webinar: SuperSpeed USB 3.0, Verification Challenges, and Solutions
The growing adoption of SuperSpeed USB (USB 3.0) is enabling some exciting new product designs, but it's also causing a big functional verification challenge. A recently archived Cadence webinar provides an overview of the USB 3.0 protocol, notes IC verification requirements and challenges, and shows...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 27 2013
DVCon 2013 Lunch Panel: Best Practices in Verification Planning
While standardized methodologies guide many other aspects of functional verification, planning the verification process is as much an art as a science. How can you know if you're following "best practices" in verification planning? One way to find out is to attend a Cadence sponsored luncheon...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Feb 14 2013
DVCon 2013 Preview – Learn from Other Design and Verification Engineers
The Design and Verification Conference ( DVCon 2013 ) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 24 2013
EE Times Webinar: Verifying ARM ACE Cache-Coherent Interconnects with UVM
Cache-coherent interconnect is a key component of any SoC that uses the ARM AMBA 4 Coherency Extension ( ACE ) specification. It's hard to design and even harder to verify. A recently archived EE Times webinar shows why cache-coherent interconnect is so complex, and explains how to build a Universal...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 5 2012
Cadence Partner Udacity Brings Higher Education to the World
On-line education pioneer Udacity is partnering with Cadence to offer an upcoming free class in functional hardware verification - but Udacity's overall mission is quite a bit broader than that. Says David Evans, vice president of education at Udacity (right): "Our mission is to make high-quality...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 26 2012
Webinar: Speeding UVM SystemVerilog Simulation With Software Engineering Techniques
You may be a software engineer and not even know it. If you develop IC verification environments, the way you write and optimize code has a tremendous impact on simulation performance. A recently archived Cadence webinar provided a number of practical tips to help you analyze and optimize Universal Verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 8 2012
DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!
In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 1 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification
Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 24 2012
Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon
DVCon, the premier conference for IC and systems verification, will be held Feb. 27- March 2 at the Doubletree Hotel in San Jose, California. This year's conference makes it clear that functional verification isn't just about digital RTL anymore. In fact, there's quite a bit of content in...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 30 2012
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