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Martin Lund CDNLive Keynote: Why SoCs Need “Application Optimized” IP
Systems on chip (SoCs) are incredibly varied, extremely complex, and based on rapidly changing requirements and specifications, according to Martin Lund, senior vice president for R&D at the Cadence SoC Realization Group. At a keynote speech at the CDNLive Silicon Valley conference March 12, 2013...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 14 2013
DAC 2012: “IP Talks!” Reveals Latest in Semiconductor IP
If you want to know what's new in the world of semiconductor intellectual property (IP), the place to be is at the IP Talks! presentations at the Cadence ChipEstimate.com booth at the Design Automation Conference ( DAC 2012 ) June 4-6. Over this three-day period, from 10:00 am to 4:30 pm each day...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 24 2012
Semico Conference: “System Driven” Semiconductor IP Leads to IP Subsystems
A "new breed" of semiconductor intellectual property (IP) is required for the next stage of evolution in the IP ecosystem, according to a keynote speech by Vishal Kapoor (right) of Cadence at the Semico Impact Conference May 16, 2012. This new type of IP will be "system driven," and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 17 2012
Q&A: Adam Traidman Updates Silicon IP Trends and ChipEstimate.com
As president and CEO of Chip Estimate before its 2008 acquisition by Cadence, Adam Traidman has been a front-row observer of the silicon IP business for many years. His company developed the InCyte chip planning tool, which includes an IP database to help designers predict area and performance. Today...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Feb 23 2012
DDR PHY Interface (DFI 3.0) Spec – Freedom of Choice for SoC Design
To implement DDR4 memory in a system-on-chip, you'll need both memory controller IP and PHY IP. If there's a standard interface between the two, you won't be locked into a particular controller/PHY combination for future designs. That's why the newly released DDR PHY Interface (DFI 3...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 19 2011
Seminar: Top 10 Essential System on Chip (SoC) Interfaces
What are the most important system on chip (SoC) interfaces that design and verification engineers need to understand? A "top ten" list presented at the August 25 Verification IP (VIP) seminar at Cadence included some old standbys and some new and emerging interface specifications. The list...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Aug 28 2011
Panelists Discuss Solutions to SoC IP Integration Challenges
Semiconductor intellectual property (IP) reuse makes system-on-chip (SoC) design possible, but complex SoCs pose some really tough IP integration challenges. Panelists at the May 12 EE Times System on Chip "Virtual Event" answered five questions posed by moderator Mike Demler, technical editor...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, May 15 2011
Jim Hogan Keynote: Making Money from SoC Realization
Veteran EDA investor Jim Hogan has a practical interest in system-on-chip (SoC) Realization, and he said so at the start of his keynote speech at the North American SystemC User Group (NASCUG) meeting today (Feb. 28, 2011). "My perspective is how I make money off this," he said. "I'm...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 28 2011
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