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Electronic System Level (ESL) Design Gets a Pragmatic Look at EDPS Workshop
Presentations at the Electronic Design Process Symposium (EDPS) April 18, 2013 gave a realistic look at the promises and limitations of electronic system level (ESL) design. Speakers noted that ESL tools are used for the lower levels of the software stack, but typically not for applications development...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 21 2013
TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies
The TSMC 2013 Technology Symposium , held April 9 in San Jose, California, brought good news for anyone interested in advanced node or 3D-IC technologies. Keynote speakers noted excellent yields and significant progress in 20nm planar, 16nm FinFET, and Chip-on-Wafer-on-Substrate (CoWoS) technologies...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 14 2013
Join EDA “Movers and Shakers” at Electronic Design Process Symposium (EDPS) April 18-19, 2013
If you're familiar with the popular, cutting-edge TED Talks lecture series, then I would call the Electronic Design Process Symposium ( EDPS ) the "TED Talks" of EDA. Now in its 20 th year, this IEEE-sponsored workshop brings together the thinkers, movers and shakers of IC and systems design...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 11 2013
IEEE Award Honors Stan Krolikoski as EDA Standards Pioneer
EDA standards are a crucial enabler of today's complex electronic design flows - and it takes a lot of hard work to create them. Few know this better than Stan Krolikoski, who got involved with VHDL standardization in the early 1980s and has taken a leadership role in standards development ever since...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Dec 3 2012
Bill Beausoleil, 1950s Computer Pioneer, Shapes RTL Emulation Technology Today
An important aspect of any advanced technology -- including the RTL emulation systems used for IC verification - is the expertise that stands behind it. Few can claim more expertise than Bill Beausoleil, an IBM, IEEE and Cadence fellow who designed some of the world's first silicon-based computer...
Posted to
Industry Insights
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by
rgoering
on Thu, Nov 15 2012
Alberto Sangiovanni-Vincentelli at ICCAD: From Early EDA to the "Sensory Swarm"
Few people have been as influential in the development of EDA as Alberto Sangiovanni-Vincentelli , professor at the University of California at Berkeley and Cadence board member. At the International Conference on Computer-Aided Design (ICCAD ) Nov. 6, he delivered a presentation that ranged from the...
Posted to
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rgoering
on Thu, Nov 8 2012
How Cadence Helps Universities Build EDA Infrastructures
Many EDA companies, including Cadence, have university programs that make it easier for academia to acquire tools. But what about the software/hardware infrastructure that supports those tools? In this era of budget shortfalls, university compute infrastructures are under severe stress. Recently the...
Posted to
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rgoering
on Wed, Nov 7 2012
Keynote: From “Tribulations” to Mixed-Signal Success at Texas Instruments
Texas Instruments has experienced many "tribulations" in mixed analog and digital design, according to Chris Collins, a director at Analog Design Services at TI. But significant progress is underway. At a keynote speech at the recent Mixed-Signal Technology Summit held at Cadence Sept. 20,...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 26 2012
Q&A: Jim Ready Discusses EDA Connection to Embedded Software Development
Few people know the embedded OS and software development tool market as well as Jim Ready - after all, he played a key role in its formation. At Ready Systems in 1981, he developed VRTX, the first commercially viable real-time operating system (RTOS). In 1999, as founder of MontaVista Software, he pioneered...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jul 16 2012
Video: Xuropa, Intel and Cadence Collaborate to Speed EDA in the Cloud
Cloud computing can generally support the types of workloads required by EDA tools, but when it comes to billion-gate semiconductor simulation, there's room for improvement. A recent collaboration between Xuropa, Intel and Cadence, presented at the user track at the June Design Automation Conference...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 27 2012
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