Home > Community > Tags > industry insights/DRAM

	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

industry insights,DRAM

TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies

The TSMC 2013 Technology Symposium , held April 9 in San Jose, California, brought good news for anyone interested in advanced node or 3D-IC technologies. Keynote speakers noted excellent yields and significant progress in 20nm planar, 16nm FinFET, and Chip-on-Wafer-on-Substrate (CoWoS) technologies...

Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 14 2013
Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic

3D-ICs that combine memory and logic promise tremendous benefits for low-power mobile applications, but design for test (DFT) remains a major concern. This week (Jan. 22, 2013) Cadence and the Belgian research institute imec are reporting progress with an automated DFT solution for memory-on-logic 3D...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jan 22 2013
MemCon Panelists Chart Future of Semiconductor Memory

Density, power, bandwidth, latency - all of these memory attributes will improve during the next few years, according to panelists at the MemCon 2012 conference Sept. 18. But don't underestimate the challenges, don't expect to replace NAND and DRAM, and forget about the dream of a "universal"...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 26 2012
MemCon Keynote: Why Hybrid Memory Cube Will “Revolutionize” System Memory

DDR3 and DDR4 aren't enough - it's time for a "revolution" in system memory that will offer exponential improvements in bandwidth, latency, and power efficiency, according to Scott Graham (right), general manager of Hybrid Memory Cube technology at Micron. In a keynote speech at the...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 19 2012
Keynote: New Memory Technologies Challenge NAND Flash and DRAM

NAND Flash and DRAM have had a great run through many process generations, but the good times for these architectures may be coming to an end, according to a keynote speaker at the Flash Memory Summit Aug. 21, 2012. Sung Wook Park, executive vice president for R&D and SK Hynix, talked about the scaling...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 22 2012
How NVM Express and 12Gb/s SAS Enable the Cloud – and Why Verification IP Helps

Two emerging protocol storage standards - Non-Volatile Memory Express (NVM Express or NVMe) and 12 Gbit/second Serial Attached SCSI (SAS) - are set to play a crucial role in the future of personal and cloud computing. As a result, Cadence has announced verification IP (VIP) support for these protocols...

Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 27 2012
The Denali Memory Report has Returned!

For more than a decade, the Denali Memory Report has been an authoritative source of information about business and technology trends in semiconductor memory and storage. The report was published by Denali Software, which was acquired by Cadence in 2010. Now the report has returned as the Denali Memory...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 5 2012
An Update on the JEDEC Wide I/O Standard for 3D-ICs

One of the big advantages of 3D-ICs with through-silicon vias (TSVs) is the potential for much faster memory bandwidth compared to conventional 2D ICs. That's why the emerging JEDEC wide I/O mobile DRAM memory standard, which takes full advantage of 3D die stacking to provide significant power and...

Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 15 2011
Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs

A major advancement in 3D-IC through-silicon via (TSV) design will be unveiled Tuesday (Dec. 13) as representatives of CEA-LETI and ST-Ericsson describe the development of a three-die stack with wide I/O memory and logic. This tapeout is the result of a collaboration between these two organizations and...

Posted to Industry Insights (Weblog) by rgoering on Tue, Dec 13 2011
ARM TechCon Paper: Why DRAM Latency is Getting Worse

There's a general view that everything gets faster and better as technology advances, but when it comes to external memory latency, that's not the case. In a recent ARM TechCon paper Marc Greenberg, director of product marketing at Cadence, showed why DRAM latency is increasing and discussed...

Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 17 2011

Page 1 of 2 (17 items) 1 2 Next >

Popular Tags

Email

Share

Subscribe

Contact Us

industry insights,DRAM

TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies

Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic

MemCon Panelists Chart Future of Semiconductor Memory

MemCon Keynote: Why Hybrid Memory Cube Will “Revolutionize” System Memory

Keynote: New Memory Technologies Challenge NAND Flash and DRAM

How NVM Express and 12Gb/s SAS Enable the Cloud – and Why Verification IP Helps

The Denali Memory Report has Returned!

An Update on the JEDEC Wide I/O Standard for 3D-ICs

Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs

ARM TechCon Paper: Why DRAM Latency is Getting Worse