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industry insights,DFM,signoff

  • Q&A: Anirudh Devgan Discusses New Cadence Signoff Strategy

    Anirudh Devgan is corporate vice president of R&D for Silicon Signoff and Verification, which is part of the Silicon Realization Group at Cadence. Last week (May 20, 2013) Cadence announced the first new product in this space, the Tempus Timing Signoff Solution . Tempus provides up to an order of...
    Posted to Industry Insights (Weblog) by rgoering on Tue, May 28 2013
  • “In Design” DFM Signoff – the Inside Story

    As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 5 2011
  • ISQED Keynote: DFM Heads in Two New Directions

    Design for manufacturability (DFM) is a fairly mature discipline that you don't hear much about these days. But a recent keynote speech outlined two interesting new developments. One new twist complements traditional model-based and rules-based approaches with pattern matching, while another brings...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 15 2011
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