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DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP
If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information. Now in its 7 th year, IP Talks! includes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 16 2013
Designer View – Using Metric-Driven Verification for Mixed-Signal IP
Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows...
Posted to
Industry Insights
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by
rgoering
on Wed, Aug 29 2012
IP Talks! Video – ARM’s John Heinlein Cites SoC Success Requirements
John Heinlein, vice president of marketing for the Physical IP division at ARM, believes that an advanced system-on-chip (SoC) design shouldn't be a "leap of faith." In a keynote speech at the IP Talks! sessions at the ChipEstimate.com booth at the Design Automation Conference (DAC 2012...
Posted to
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rgoering
on Tue, Jul 10 2012
Panel: Integrating Low-Power ARM Processors into Mixed-Signal Designs
Mixed-signal chip designs with embedded digital signal processing are becoming more and more commonplace these days. How can you bring low-power processors, such as the ARM Cortex-M0 , into such designs quickly and efficiently? A lunch panel discussion at the recent Design Automation Conference (DAC...
Posted to
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rgoering
on Wed, Jun 20 2012
DAC 2012 IBM Keynote: Multi-Core Performance Growth Slowing, New Approaches Needed
In the early 2000s we hit a power "wall" and decided to scale it by putting multiple processor cores on a single chip. But the multi-core era is running into limitations, and it's time to start planning for a "new era" in which design innovation will fuel performance growth, according...
Posted to
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rgoering
on Sun, Jun 10 2012
12 Hot EDA Topics – 78 DAC Demo Sessions
Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday...
Posted to
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on Thu, May 24 2012
DAC 2012: “IP Talks!” Reveals Latest in Semiconductor IP
If you want to know what's new in the world of semiconductor intellectual property (IP), the place to be is at the IP Talks! presentations at the Cadence ChipEstimate.com booth at the Design Automation Conference ( DAC 2012 ) June 4-6. Over this three-day period, from 10:00 am to 4:30 pm each day...
Posted to
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on Thu, May 24 2012
Digital and Analog Verification – Round Peg in a Square Hole?
Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different...
Posted to
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rgoering
on Thu, Feb 9 2012
Panel Video: Preventing IP Theft in a Global Market
How can semiconductor companies ensure IP integrity in a global marketplace? Are foundries liable if customers use stolen semiconductor IP? Do systems companies really care if their semiconductor IP is stolen? These are some of the questions that emerged at a Design Automation Conference panel in June...
Posted to
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rgoering
on Thu, Aug 4 2011
Video: IP Ecosystem Helps Xilinx Become a “Platform Provider”
Xilinx is making a shift from being a silicon provider to a platform provider, according to David Tokic, director of partner ecosystem alliances at Xilinx. As such, the company is increasingly relying on a broad ecosystem that includes silicon IP, EDA, and services. In a video interview at the recent...
Posted to
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on Mon, Jun 20 2011
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