Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> industry insights/Cadence/emulation
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
industry insights,Cadence,emulation
48th DAC
acceleration
Altera
ARM
Beausoleil
Berkeley Wireless Research Center
bring-up
broadcom
build or buy
build vs. buy
BWRC
CAD
ChipEstimate
cloud computing
computer history
DAC
DAC 2011
DAC: DAC panel
Denali Party
DVCon
EDA
EDA360
EE Times
embedded software
emulator
ESL
Fairchild
Fluxx
FPGA prototyping
FPGA-based emulation
FPGA-based prototypes
FPGA-based prototyping
FPGAs
Freescale
Gene Amdahl
Gordon Moore
graphical design
hardware/software co-development
hardware/software integration
hardware-assisted verification
I Love DAC
IBM
IEEE
Incisive
Intel
IP
Jaeger
low power
low power panel
Low Power Summit
mainframes
Palladium
Panel
power architectures
power estimation
power management
Power Modeling
processor-based emulation
prototyping
prototyping vs. emulation
Qualcomm
Quartus
Quickturn
rapid prototyping
Rapid Prototyping Platform
RPP
RTL emulation
Schirrmeister
silicon computers
Simpson
Simulation
software
software development
Springsoft
Stanford
Stratix
Synopsys
System Development Suite
system realization
System/360
system-level
verification
Verification Computing Platform
virtual platforms
virtual prototoyping
virtual prototype
virtual prototypes
virtual prototyping
Virtual System Platform
webinar
workshops
Xilinx
Bill Beausoleil, 1950s Computer Pioneer, Shapes RTL Emulation Technology Today
An important aspect of any advanced technology -- including the RTL emulation systems used for IC verification - is the expertise that stands behind it. Few can claim more expertise than Bill Beausoleil, an IBM, IEEE and Cadence fellow who designed some of the world's first silicon-based computer...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Nov 15 2012
Panelists: Low Power Design Needs System-Level Boost
When low-power design experts get together, much of the conversation turns to the system level. At least that was the case at the recent Low Power Technology Summit held at Cadence Oct. 18, 2012, where audience members questioned panelists about early power estimation, power modeling, and the role of...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Oct 28 2012
DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?
Emulation and FPGA-based prototyping are becoming increasingly necessary for complex systems-on-chip, but where are these hardware-assisted tools going to come from? Should you invest the resources to build and maintain your own, or purchase a commercially available solution? In either case, what do...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 7 2012
Webinar: Easing the Pain of FPGA-Based Prototyping
Nearly every digital system-on-chip, ASIC or ASSP is prototyped in FPGAs, most typically for pre-silicon software development and debugging. The problem is that it can take months to get the prototype up and running with a functionally equivalent design. But there are easier ways to develop FPGA-based...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Sep 8 2011
DAC Panel Calls Off “Battle” Between Prototyping and Emulation
A Design Automation Conference (DAC) panel June 8 looked like it was destined for controversy. It was titled, "Software-Hardware Verification Battle: Prototyping vs. Emulation." But that battle didn't happen. Instead, most participants agreed that several types of hardware/software integration...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jun 14 2011
Cadence System Development Suite – The Story is the Continuum
Cadence today (May 3) is introducting the System Development Suite , a set of four connected platforms that support hardware/software co-development from the architectural level through final prototyping. The story is not just that Cadence now has solutions for virtual prototyping and FPGA prototyping...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 3 2011
Cadence at DAC 2011 – And Denali Party Update
The 48 th Design Automation Conference ( DAC ) is just a little over one month away, and Cadence will have a substantial presence on the exhibit floor, in panel sessions, and in co-located workshops. Of course, the famous Denali Party is a highlight, and it is on! A new Cadence DAC microsite located...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 2 2011
Page 1 of 1 (7 items)