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industry insights,Cadence,ARM

EDA CEOs Reveal Thoughts About Present and Future of EDA Industry

At an EDA Consortium ( EDAC ) panel discussion March 14, 2013, top executives from Cadence, Mentor, Synopsys, ARM, and EDA startup Nimbus shared their views about a range of business and technology issues facing the EDA industry. Panelists engaged in lively discussions about topics including consolidation...

Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 18 2013
Samsung CDNLive Keynote: Innovation and Challenges in the Post-PC Era

We are living through a "disruptive" transition in which a PC-driven market is giving way to a mobile-driven market, according to Young Sohn, president and chief strategy officer for device solutions at Samsung Electronics. In a keynote speech March 12, 2013 at the CDNLive Silicon Valley conference...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 13 2013
Common Platform Forum Keynotes: 14nm FinFETs and Beyond

How far can we continue to scale semiconductors? 14nm FinFET technology is the next major move, but that's far from the end of the story, according to keynote speakers at the Common Platform Technology Forum in Santa Clara, California Feb. 5, 2013. The keynotes, still available for on-line viewing...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 6 2013
BSIM-CMG FinFET Model – How Academia and Industry Empowered the Next Transistor

A 3D multi-gate transistor called the FinFET promises tremendous power and performance advantages at 16nm and 14nm process nodes (and was adopted at 22nm by Intel) -- but nobody can use FinFETs without an accurate compact model. Fortunately, the BSIM-CMG model available from the University of California...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 21 2013
Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

A recent test chip tapeout using the Samsung 14nm FinFET process revealed significant progress in digital implementation at this new process node. Thanks to deep collaboration and extensive R&D investments in libraries, process, and tools, the digital implementation of the test chip was successfully...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 7 2013
Webinar Report: Assertion-Based Verification IP Ensures ARM ACE Protocol Compliance

Do you want to enjoy the benefits of formal verification without having to become an expert? A newly archived Cadence webinar shows how you can do just that, using assertion-based verification IP (ABVIP) that supports both formal and dynamic verification of systems-on-chip using the ARM ACE protocol...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 19 2012
Video, Presentation – Low Power Design with ARM Physical and Processor IP

Most system-on-chip designers have two things in common - use of ARM physical and/or processor IP, and a mandate to reduce power consumption. There's a wealth of information on low-power design with ARM IP in a newly available video, as well as presentation slides, from an hour-long presentation...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 17 2012
ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip

All 20nm test chips are learning experiences, and a recent tapeout of a 20nm Cortex-M0 test chip by ARM engineers was no exception. Completed in June 2012, the test chip design used a Cadence digital implementation flow. The story of the test chip is told in a new guest partner blog (I'm the "guest"...

Posted to Industry Insights (Weblog) by rgoering on Tue, Nov 27 2012
ARM TechCon: Inside Story of a 14nm FinFET Tapeout

The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 31 2012
Panelists: Low Power Design Needs System-Level Boost

When low-power design experts get together, much of the conversation turns to the system level. At least that was the case at the recent Low Power Technology Summit held at Cadence Oct. 18, 2012, where audience members questioned panelists about early power estimation, power modeling, and the role of...

Posted to Industry Insights (Weblog) by rgoering on Sun, Oct 28 2012

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industry insights,Cadence,ARM

EDA CEOs Reveal Thoughts About Present and Future of EDA Industry

Samsung CDNLive Keynote: Innovation and Challenges in the Post-PC Era

Common Platform Forum Keynotes: 14nm FinFETs and Beyond

BSIM-CMG FinFET Model – How Academia and Industry Empowered the Next Transistor

Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

Webinar Report: Assertion-Based Verification IP Ensures ARM ACE Protocol Compliance

Video, Presentation – Low Power Design with ARM Physical and Processor IP

ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip

ARM TechCon: Inside Story of a 14nm FinFET Tapeout

Panelists: Low Power Design Needs System-Level Boost