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industry insights,28nm,DRC+

  • ARM TechCon Address: High Stakes at Low Process Nodes

    The complexity of advanced-node IC designs is skyrocketing, and the demands on EDA tool development seem overwhelming - but innovation and deep collaboration will break through the challenges, according to Chi-Ping Hsu, senior vice president for R&D at the Silicon Realization group at Cadence. In...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 25 2011
  • “In Design” DFM Signoff – the Inside Story

    As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 5 2011
  • Analog/Mixed-Signal at 28nm – An Inside Look

    A common belief is that "analog doesn't scale." But analog/mixed-signal design can indeed work at advanced process nodes. An inside look into how, and what the challenges are, comes from a recent partnership between GLOBALFOUNDRIES and Cadence that produced a 28nm analog/mixed-signal design...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 8 2010
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