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industry insights,20nm,Samsung,20 nm

  • Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

    In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...
    Posted to Industry Insights (Weblog) by rgoering on Mon, May 7 2012
  • Free Webinars Preview 20nm Challenges, Solutions

    If you're designing or planning to design at 20nm - or you're just curious about this emerging and much-discussed process node - three free webinars May 1, 2 and 3 will provide a wealth of valuable information. In these webinars, Cadence experts will team up with industry leaders to present 20nm...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Apr 12 2012
  • ARM TechCon Paper: Inside Story of a 20nm Test Chip Tapeout

    In March 2011, ARM, Cadence and Samsung launched a collaborative effort to design a 20nm test chip based on nanoSTEP (nSTEP), a microcontroller reference platform based on the ARM Cortex-M0 processor. This chip taped out just two months later and was formally announced in July . At the recent ARM TechCon...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 8 2011
  • DAC Panel: 20nm is Tough, But Not a Roadblock

    So far the move to lower semiconductor process nodes has continued unabated, but the upcoming 20nm node is causing a lot of concern. Lithography is so challenging that extra masks ( double patterning ) will be required. Will designs be technically and economically feasible? Panelists at the Design Automation...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 6 2011
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