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industry insights

  • Behind Accellera’s Vote For OVM-Based Standardization

    As noted in a recent Cadence blog by Tom Anderson, the Accellera Verification IP (VIP) Technical Subcomittee has voted to make the Open Verification Methodology ( OVM ) the basis of its upcoming “Universal Verification Methodology” (UVM) standard. Here are some thoughts about what this means...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 7 2010
  • Q&A: Michał Siwiński Sees Major Shift in Product Design and Verification

    The rising costs of product development are causing fundamental changes in the design and verification flows, according to Michał Siwiński, group director of front-end product management at Cadence. In this interview he discusses customer challenges and Cadence strategies in such areas as hardware/software...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 6 2010
  • EDA Outlook 2010: A Cost-Driven Market

    The worst recession of modern times may be over, but the changes it is leaving in its wake will persist. For surviving semiconductor and systems companies, a new top priority has emerged – controlling and reducing both design costs (implementation and verification) and chip costs (such as die size...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 4 2010
  • Notable EDA Blog Postings For 2009

    This is the time of year when everybody has lists – and here’s one that may be a little different. Below are some notable blog postings from various external (non-Cadence) blogs in 2009. They’re listed in chronological order with no ranking implied. After listing one interesting posting...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 28 2009
  • Top EDA Standards Efforts To Watch In 2010

    There’s some good news for the New Year – it looks like 2010 will be a busy year for EDA-related standards development. Here’s a short list of significant standards efforts (alphabetical by standards body, no implied ranking) that are expected to yield some interesting results in the...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 21 2009
  • Debug Emerges As Biggest Verification Bottleneck

    We’ve all heard that functional verification takes 60 to 70 percent of the design cycle, but what’s not often discussed is what, exactly, takes up all that verification time. For a growing number of design and verification teams, the biggest single bottleneck is the time spent diagnosing...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 17 2009
  • Intel TV Interview: Parallelizing Legacy EDA Applications

    Can EDA vendors parallelize millions of lines of legacy code, or do they need to rewrite everything in order to run on multicore and many-core platforms? In a Dec. 8 interview for Intel Software Network TV , Tom Spyrou, distinguished engineer at Cadence, described how legacy code can be parallelized...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 16 2009
  • Q&A Interview: New IEEE DASC Chair Discusses EDA Standards

    Stan Krolikoski, group director for standards and ecosystems at Cadence, has been elected chair of the IEEE Design Automation Standards Committee ( DASC ), which oversees all EDA-related IEEE standards activities. In this interview he discusses the role of the DASC, identifies key 2010 EDA standards...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 14 2009
  • Preparing The Next Generation Of IC Designers

    While many universities offer classes in VLSI design, it is very difficult for universities to turn out graduates who can go right to work as chip designers. As a result, there’s a looming shortage of engineers in key areas such as RF, mixed-signal and verification. How can this gap between academia...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 10 2009
  • User Interview: Forging A Multi-Mode Synthesis Flow

    Traditional synthesis flows aren’t keeping up with IC complexity and low-power demands, according to Laszlo Borbely, design engineer at Micron Technology . At the recent CDNLive! Silicon Valley , Borbely discussed a new flow that uses concurrent multi-mode synthesis and low-power optimization based...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 9 2009
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