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Xilinx
Q&A Interview: Kaufman Award Winner Discusses Verification Advances
Dr. Randal Bryant , Dean of Computer Science at Carnegie-Mellon University, will receive the EDA industry’s highest honor – the Phil Kaufman award – in November for his pioneering work in formal verification and simulation. In this interview, he answers questions about his past contributions...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 5 2009
User Interview: The Case For High Level Synthesis
One way to gauge the quality of high-level synthesis is to run it on an existing design, and compare the synthesized RTL with the previously hand-generated RTL in power, performance and area. The Industrial Technology Research Institute (ITRI), a Taiwanese research center, recently did just that with...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Oct 1 2009
Cadence’s Xuropa Experience – A New Approach To IP Evaluation
Evaluating EDA software or silicon IP is an arduous process that often requires negotiated license agreements, software downloads, installation, and the physical presence of a jet-lagged AE who just flew across the country. What if you could run an evaluation instantly on line, and skip all that? That’s...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 30 2009
Q&A Interview: Steve Carlson Discusses Cadence Mixed-Signal Strategy
Steve Carlson is vice president of marketing for low power and mixed-signal solutions at Cadence. In this interview, he discusses the increasing importance of mixed-signal SoCs, describes key challenges, and outlines Cadence strategy and solutions. Q: The term "mixed signal" has been around...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 28 2009
Are SoC Development Costs Significantly Underestimated?
A stark warning about SoC development costs was sounded in a panel discussion on the “Economics of Next Generation SoCs” at the recent EE Times virtual System-on-Chip Conference . Development costs are not only high, said Ron Collett, CEO of Numetrics , but are “significantly underestimated”...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Sep 24 2009
CDN Live! Silicon Valley -- A Video Invitation From Cadence CMO John Bruggeman
CDNLive! Silicon Valley , the largest of the CDNLive! Cadence user conferences, will be open for worldwide participation in 2009. This year’s conference is a webinar-based event that allows on-line participation as well as on-site attendance at Cadence’s San Jose, California headquarters...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 23 2009
Impressions From A “Virtual” SoC Conference
I attended portions of an EE Times “virtual” system-on-chip (SoC) conference last week, and came away with some observations that I’d like to share. There is some irony here. After years of writing about Cadence and other EDA vendors for EE Times, I am now reporting about an EE Times...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 21 2009
User Interview: Running Full Chip Mixed-Signal Simulations
Running full-chip, mixed-signal simulations with sufficient accuracy and speed is a huge challenge for system-on-chip (SoC) designers. But engineers at SiRF , a provider of GPS chipsets and subsystems, have been able to do so, according to Marcelo Silva, verification engineer. In an interview at the...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Sep 17 2009
Building an SOI IP/EDA Infrastructure
My last blog on silicon-on-insulator looked at the low-power benefits of SOI. But performance and power gains are meaningless if you can’t design and manufacture a chip. Fortunately, the needed infrastructure to support SOI design is falling into place. As the SOI Consortium noted in a Design Automation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 16 2009
Green Electronics – Is SOI The Answer?
Silicon-on-insulator (SOI) technology has been used primarily for performance-hungry applications that can justify the additional wafer cost. The SOI Consortium recently launched a “ Simply Greener ” campaign to promote SOI for power savings. While SOI can substantially reduce power consumption...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 14 2009
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