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  • Re: [Help]Issues regarding Extraction

    Hi Andrew, Thanks for your advice,Still I have some doubts... Tool version: cadence IC614,ASSURA410,MMSIM 101 I am using two scripts to invoke tool,in that certain variables are used to set lib paths.After invoking tool,Library viewer shows paths are valid and in that analogLib mapped into IC614.But...
    Posted to RF Design (Forum) by hsps on Tue, Sep 10 2013
  • [Help]Issues regarding Extraction

    Hi Friends, I'm facing some issues while doing Extraction including inductances,like ERROR: Failed to find a cellview for (pinductor) ERROR: Failed to find a cellview for (pmind) ERROR: Failed to find a cellview for (vsource) ERROR: Failed to find a cellview for (ccvs) But its working properly for...
    Posted to RF Design (Forum) by hsps on Tue, Sep 10 2013
  • Any symbol for simulation of mutual induction between two inductors?

    While placing parts, I cannot find a part which I can use to simulate 2 inductors in mutual induction with each other. Is anything similar there? I feel like this software was created with the idea of giving utmost pain to the users.
    Posted to Functional Verification (Forum) by Abhimanyu1 on Thu, Sep 20 2012
  • Re: custom inductor/tline layout Assura LVS issue

    I figured this out, the cause is that pinLayer definition in extract.rul is missing, the file require a few edits, relevant informantion can be found in Assura Developer Guide. Thanks for your attention. If you have trouble with this too, I'd be gald to help out. Ran
    Posted to RF Design (Forum) by snaildr on Wed, May 2 2012
  • Inductor Layout

    Hi guys Recently, I'm drawing the inductor in the layout. My procedure to do this is, first drawing a ring, second convert it to polygon. But I find it is not very convenient since after you convert the ring into the polygon the width of the metal can't be changed. Could someone know how to solve...
    Posted to RF Design (Forum) by Henrytqy on Wed, Apr 18 2012
  • How is s-parameter simulation done in Cadence virtuoso?

    I want to know how s-parameters are calculated in Cadence virtuoso sp simulation? Is their a document explaining the same? I am simulating three versions of a TSMC kit inductor with different lengths of interconnect connected to it. I extract their layouts using Calibre and then do a s-parameter simulation...
    Posted to RF Design (Forum) by hmcheema on Thu, Dec 15 2011
  • Custom Inductor | INDDEF layer | HitKit | Assura

    Hi, this post isin reference to http://www.cadence.com/community/forums/T/14022.aspx , where i described problems concerning an inductor that had been automatically generated by VPCD tool. Defining the layout of the inductor as a blackBox does not solve the problem, for assura does not recognize pins...
    Posted to Custom IC Design (Forum) by pitter on Tue, Dec 1 2009
  • ASSURA LVS error | Custom Inductor | Pin mismatch | Unbound devices

    Hi, I have generated a inductor Ind1 with a Passive Component Designer (PCD) tool. The inductor is used in LC VCO schematic.After LVS run I get the following errors and discrepances: 1)Error: Ind1(Generic) on Schematic is unbound to any layout device 2)in LVS report I get that pins of the inductor are...
    Posted to Custom IC Design (Forum) by pitter on Fri, Nov 13 2009
  • Re: ROD example

    By "transformer" are you talking about a layout which has overlapping or adjacent coils, such as those for an inductor? Could you use an inductor as a starting point for this? There is Solution 1809475 on SourceLink for a Spiral Inductor. Oh, while I was looking at that Solution, I noticed...
    Posted to Custom IC SKILL (Forum) by skillUser on Mon, Oct 5 2009
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