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  • System-level Low Power Techtorials/Workshops Off To A Great Start!

    Back in my 24 March blog I mentioned how Cadence was kicking off a major techtorial/workshop series across North America on low power chip design, using the newest Cadence tools at the ESL/System/Chip Architecture level. Last week we concluded the first three events, all in California: Irvine, San Diego...
    Posted to System Design and Verification (Weblog) by SteveSvoboda on Mon, Apr 20 2009
  • Friday Fun: Caveman Finds Cadence

    For those of you new to this series that want to come up to speed quickly, the best bet is to check out the "Notes" for each episode over on the "The Next Generation" Facebook page . Become a fan! After last week's desparation move by Charlene, the team realizes they need to do...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Apr 10 2009
  • There's Still Life at 130 nm and Above

    Previously unpublished data from ChipEstimate.com suggests that design activity at the 130 nm and 180 nm process nodes remains very strong, despite a recent upsurge in interest in 65 nm. This data has some interesting implications for EDA, silicon IP, and foundry providers, as well as IC design teams...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 7 2009
  • New InCyte v3.5 Let’s You Manage Power, Without Being the “Power Expert”

    Quantify the trade-offs of Power Management techniques in Early Chip Planning with the new v3.5 release of Chip Planning Solutions . The Chip Planning Solutions team, who comes to Cadence via acquisition of ChipEstimate.com about one year ago, has just released a new version of InCyte . You may be familiar...
    Posted to Logic Design (Weblog) by Mike Carrell on Fri, Apr 3 2009
  • My Twitter Experiment - Just Follow Me

    "I didn't know that Conformal ECO-physical was released. When did that happen? Which version of LEC?" , said one of my customers said recently. I have a lot of customers who ask about the latest product information once in a while. I see my peeps at seminars, customer visits, workshops...
    Posted to Logic Design (Weblog) by Kenneth Chang on Tue, Mar 24 2009
  • Moving Low Power Chip Design up to the System Level

    Anybody watching Cadence these past couple years has probably noticed how we're pretty serious about investing in making tools for low-power design. While most of the attention in the EDA industry up to now has been on how to optimize chip power consumption while working at the RTL/gate level, that...
    Posted to System Design and Verification (Weblog) by SteveSvoboda on Tue, Mar 24 2009
  • When Green Chips Turn Brown

    I went to New York City last weekend and went to see a Broadway show called Avenue Q. It's a very adult adaption of Sesame Street (sort of). Before you grab a bus, plane, or train to NYC to see this show with your kids, be forewarned. Puppets aside, this is NOT a show for children. And while that...
    Posted to Logic Design (Weblog) by jflieder on Thu, Nov 20 2008
  • Why Should I Use a Floorplan for Physical Prediction and Synthesis?

    It goes without saying that performing logical synthesis without timing or power constraints is of limited value at best. The netlist that is painstakingly crafted by a synthesis tool is very much tied to a particular set of constraints. Cell function and sizes have been selected to meet the timing targets...
    Posted to Logic Design (Weblog) by mrardon on Tue, Nov 4 2008
  • Chip Planning at Blazing Speeds with Incyte!

    I'm sooo pumped up about this new chip planning tool we acquired 6 months ago. Out of all the Cadence tools, this is definitely one of the hottest stuff according to customer feedback - it has the potential to change the way ASIC engineers and managers work because of the X factor in productivity...
    Posted to Logic Design (Weblog) by Kenneth Chang on Thu, Oct 9 2008
  • "I hate spreadsheets"

    So, as customer after customer visited the ChipEstimate booth on Oct. 1 (a tool for early chip planning as well as providing huge easy access to 1000's of IPs from 100's of 3rd party vendors for chip proto-building) during the very successful Power Forward Initiative (PFI) event in San Jose,...
    Posted to Logic Design (Weblog) by Kenneth Chang on Fri, Oct 3 2008
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