Home > Community > Tags > incyte/Industry Insights
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

incyte,Industry Insights

  • Q&A: Adam Traidman Updates Silicon IP Trends and ChipEstimate.com

    As president and CEO of Chip Estimate before its 2008 acquisition by Cadence, Adam Traidman has been a front-row observer of the silicon IP business for many years. His company developed the InCyte chip planning tool, which includes an IP database to help designers predict area and performance. Today...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 23 2012
  • ISQED Keynote: Putting Some Numbers To Cost-Aware Design

    We've all heard about the escalating costs of system-on-chip (SoC) development. But what are the costs, and what are the potential savings? Steve Glaser, corporate vice president of strategic development at Cadence, filled in some of those numbers at a keynote speech March 24 at the International...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 29 2010
  • A Critical Step In The IC Design Flow

    Every IC design team does it. Most don’t have a name for it and most don’t use automated tools. It may not show up on flowcharts depicting the IC design flow, and most EDA vendors pay little attention to it. But it’s an absolutely critical part of the IC design flow that can make the...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 14 2010
  • User Interview: How To Estimate Power Early

    Early power estimation makes it much easier to manage IC power, according to Camille Kokozaki, director of design automation services at Integrated Device Technology ( IDT ). At the recent CDNLive! Silicon Valley , he presented a case study of architectural power estimation with a 65nm system-on-chip...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Oct 29 2009
  • There's Still Life at 130 nm and Above

    Previously unpublished data from ChipEstimate.com suggests that design activity at the 130 nm and 180 nm process nodes remains very strong, despite a recent upsurge in interest in 65 nm. This data has some interesting implications for EDA, silicon IP, and foundry providers, as well as IC design teams...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 7 2009
Page 1 of 1 (5 items)