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incisive,UVM

New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release...

Posted to Low Power (Weblog) by Adam Sherilog on Tue, May 7 2013
IBM and Cadence Collaboration Improves Verification Productivity

Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy verification technologies and methodologies to improve...

Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Feb 13 2013
Webinar Report: Assertion-Based Verification IP Ensures ARM ACE Protocol Compliance

Do you want to enjoy the benefits of formal verification without having to become an expert? A newly archived Cadence webinar shows how you can do just that, using assertion-based verification IP (ABVIP) that supports both formal and dynamic verification of systems-on-chip using the ARM ACE protocol...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 19 2012
Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

In today's complex SoCs, early performance analysis and verification of SoC interconnect is crucial. Architects must ensure that interconnect will meet the bandwidth and latency requirements of the target application, while verification engineers must build a testbench that assures functional correctness...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 9 2012
The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos. Interface UVC Environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Sep 4 2012
Designer View – Using Metric-Driven Verification for Mixed-Signal IP

Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 29 2012
Webinar: Speeding UVM SystemVerilog Simulation With Software Engineering Techniques

You may be a software engineer and not even know it. If you develop IC verification environments, the way you write and optimize code has a tremendous impact on simulation performance. A recently archived Cadence webinar provided a number of practical tips to help you analyze and optimize Universal Verification...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 8 2012
Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Ernie & Duracell "I feel great" - long pause - "I feel great, I feel great". 6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great". I hear this sound coming out of my son's room. What is going on in my house? Is there such a...

Posted to Functional Verification (Weblog) by Axel Scherer on Wed, Aug 1 2012
Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese

A little over two and a half months ago we started sounding the "cowbell" with the release of the UVM SystemVerilog Basics videos . The resonance has been strong. As there can (almost) never be too much of a good thing, we are expanding this series by re-releasing the videos audio dubbed into...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, Jul 23 2012
UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action

Just after releasing the original cowbell video series I found that Ben and Jerry's had discovered a great way to combine cowbells and charity. In April of this year, they held an event for a new world record of over 1600 cowbells in action . It is a must see for the cowbell aficionado. Coincidentally...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, Jul 16 2012

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incisive,UVM

New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

IBM and Cadence Collaboration Improves Verification Productivity

Webinar Report: Assertion-Based Verification IP Ensures ARM ACE Protocol Compliance

Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

Designer View – Using Metric-Driven Verification for Mixed-Signal IP

Webinar: Speeding UVM SystemVerilog Simulation With Software Engineering Techniques

Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese

UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action