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incisive,IP-XACT

Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

In today's complex SoCs, early performance analysis and verification of SoC interconnect is crucial. Architects must ensure that interconnect will meet the bandwidth and latency requirements of the target application, while verification engineers must build a testbench that assures functional correctness...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 9 2012
Webinar Report: How Formal “Apps” Ease IC Verification

Formal verification applications, or "apps," can significantly lighten the IC verification workload without requiring a knowledge of assertion-based verification (ABV) - or even, in most cases, the need to write assertions. A recently archived Cadence webinar , held Aug. 8, 2012, describes...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 16 2012
Update to the OVM Register Package

OVM users have something new to give thanks for this holiday season -- an update to the OVM Register Package (new link!!). This package is used by novice and advanced users and embodies years of experience gathered through hundreds of SystemVerilog projects. The Cadence genIES team has been remiss since...

Posted to Functional Verification (Weblog) by Team genIES on Tue, Nov 29 2011
Video: Duolog at DAC 2011 Update – Automating Design and Verification IP Integration

One of the key tenants of the EDA360 vision is the need for scalable, correct-by-construction IP creation and integration of design and verification IP. Duolog is in the vanguard of creating automation to address this challenge, and in this video update Duolog's CTO Dave Murray notes new capabilities...

Posted to Functional Verification (Weblog) by jvh3 on Sun, Jun 26 2011
Webinar: How IP-XACT Standard Supports TLM Flow

As the EDA360 vision paper notes, tool and methodology support is needed for IP integration into systems-on-chip (SoCs). A standards-based ecosystem needs to be part of this approach. One standard that can play an important role is IP-XACT, which provides a metadata documentation format for packaging...

Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 1 2011
ESL Design - SystemC TLM2 IP Authoring: A Practical Experiment

Introduction ESL Virtual Platforms (systems or sub-systems) require heterogeneous libraries of TLM IP models that can interconnect. Indeed, the OSCI TLM2 interfaces appear to be the only viable solution to solve this interoperability issue. Moreover the IP you need is not always available (because it...

Posted to System Design and Verification (Weblog) by TeamESL on Thu, Feb 26 2009

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incisive,IP-XACT

Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

Webinar Report: How Formal “Apps” Ease IC Verification

Update to the OVM Register Package

Video: Duolog at DAC 2011 Update – Automating Design and Verification IP Integration

Webinar: How IP-XACT Standard Supports TLM Flow

ESL Design - SystemC TLM2 IP Authoring: A Practical Experiment