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in-design signoff,Industry Insights,DFM

  • Q&A: Anirudh Devgan Discusses New Cadence Signoff Strategy

    Anirudh Devgan is corporate vice president of R&D for Silicon Signoff and Verification, which is part of the Silicon Realization Group at Cadence. Last week (May 20, 2013) Cadence announced the first new product in this space, the Tempus Timing Signoff Solution . Tempus provides up to an order of...
    Posted to Industry Insights (Weblog) by rgoering on Tue, May 28 2013
  • ISQED Keynote: 20nm From a Custom/Analog Perspective

    Most of the discussions about the upcoming 20nm process node have focused on digital design. Not so at the International Symposium on Quality of Electronic Design ( ISQED 2012 ) March 20, where Tom Beckley, senior vice president of R&D for Custom IC and Signoff in the Silicon Realization group at...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 21 2012
  • SPIE Papers Showcase DFM and Lithography R&D

    Ten Cadence papers planned for the upcoming SPIE Advanced Lithography conference, set for Feb. 12-16 in San Jose, California, demonstrate recent R&D developments in both "design side" design for manufacturing (DFM) and the computational lithography that takes place during the manufacturing...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 26 2012
  • “In Design” DFM Signoff – the Inside Story

    As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 5 2011
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