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  • How to not netlist a certain symbol

    Good day! I want to make library that when added to schematic, the instances are not netlisted during spectre simulation. The symbols does not have models and are designed for CDF parameter extraction only. I have a reference LIBRARY with this property but I can not find out how it was implemented. I...
    Posted to Custom IC SKILL (Forum) by alainmelan on Thu, Jul 3 2014
  • 2 layers by 1 bindkey

    Could any one tell me how can we toggle the visibility of two ( or more ) layers [ Layer 1, 2, 3 .. ] using a single bindkey ?
    Posted to Custom IC SKILL (Forum) by shazzy on Tue, Apr 2 2013
  • Virtuoso GDS Via Problem

    Hi! I'm having problems with vias, which are exportet to GDS files. I exportet the chip layout from Encounter to a GDS file: streamOut chip.gds.gz -mapFile ../setup/gds2.map -libName DesignLib -stripes 1 -units 1000 -mode ALL The GDS file is hierarchical and instanciates standard cells, io pad cells...
    Posted to Custom IC Design (Forum) by Johann Glaser on Tue, Aug 16 2011
  • GCC_3.3.1 error while invoking icfb 5141

    Hi, Thanks in advance! When I invoke the tool from /opt/cadence/ic5141/tools/dfII/bin/icfb I get following error: [root@localhost sf_Cadence]# icfb & [1] 17463 [root@localhost sf_Cadence]# /bin/sh: /opt/cadence/ic5141//tools/lib/libgcc_s.so.1: version `GCC_3.3.1' not found (required by /bin/sh...
    Posted to Custom IC Design (Forum) by kdev on Wed, Jul 13 2011
  • Using Spice Models/Netlists with icfb

    Hi all, I'm pretty new to the Cadence Environment and now I've got the task to make some simulations including some commercial PSpice models within the Cadence Environment (icfb, Virtuoso etc.). I found some information on the internet saying that this task could be done using "CDL in.....
    Posted to Custom IC Design (Forum) by mixedsignal on Tue, Dec 7 2010
  • CIW > File > Import > Verilog... fails to create schematics (portOrder property?)

    Hello I try importing the final verilog (.v) file generated by SoC encounter so I can do LVS for a mixed signal design, but ihdl.exe doesn't generate schematics. The beginning of the log file says (scgp is the digital library name in icfb): @(#)$CDS: ihdl.exe version 5.1.0 12/16/2007 23:32 (cicln04...
    Posted to Custom IC Design (Forum) by skylerweaver on Fri, Feb 12 2010
  • vdd not sensed in post-layout simulation

    Hi, I tried to do post layout simulation with extracted, symbolized inverter, however, I got the message during simualtion: Notice from spectre during topology check. Only one connection to node 'vdd!' I plot the output and confirmed that vdd is not applied to the internal transistors of the...
    Posted to Custom IC Design (Forum) by Malolo on Tue, Jan 12 2010
  • mapping file

    Help me how to use the mapping file to change the cells from one library to other library. In CIW -> ****_tools->Rereference standard cells is there any extension for the map file. It will be helpful with explanation how it will work and how to use. Regards Sathisha
    Posted to Custom IC Design (Forum) by sathisha on Tue, Jan 5 2010
  • How to customize icfb start-up with 2 monitors?

    I have just started working with a 2 monitor PC system. I am running Windows XP locally, and connecting to the Linux server over XMing, or PuTTy. When I start icfb, the CIW and all pop-ups from the CIW are placed between the 2 monitors, as opposed to either the right or left monitor. How do I rectify...
    Posted to Custom IC Design (Forum) by AdamDaniels on Thu, Jul 23 2009
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