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help

  • OrCAD capture Netlisting error

    Hi, Just wondering if anyone can help me out. I'm trying to simulate a schematic into PSpice but I keep gettting this message: Creating PSpice Netlist INFO(ORNET-1041): Writing PSpice Flat Netlist .\ Cannot remove file .\ ERROR Unable to create netlist file. Any Idea what this might be. I have a...
    Posted to Feedback, Suggestions, and Questions (Forum) by Lulaz on Tue, Mar 26 2013
  • How To: Bring Up Encounter "man" Pages from a UNIX Prompt

    Okay, this one is too cool not to share. The other day a customer and I were trying to understand a tool behavior better so we did what we all do in desperate times: We read the documentation. As straightforward as "reading the documentation" would seem, I bet no two users of the system interact...
    Posted to Digital Implementation (Weblog) by BobD on Wed, Aug 1 2012
  • ncverilog simulation overflow

    hi, i am new here. I have a problem as below when i do my design simulation: 4038444601 Overflow Simulation stopped via $stop(1) at time 40384446008 PS + 2 how could this happens? thanks! and my timescale is 1ns/10ps
    Posted to Custom IC Design (Forum) by dzkxybx on Sun, Jun 24 2012
  • how to recover a locked simulation on the Cadence server?

    Hello, I am using Cadence 5.10.41 , I want to know that if I am running a simulation on my Cadence server, which is being accessed through PuTTy on my PC, after a power breakdown on my PC (my server has no power breakdown), I access the PuTTy and I find out that the process has been locked and is not...
    Posted to Custom IC Design (Forum) by sohaibafridi on Tue, Apr 17 2012
  • Five-Minute Tutorial: Encounter Command Line Help

    Hi everyone, and welcome to the first Five-Minute Tutorial! I have several things planned for this series. Today we're going to look at getting help on the command line in the Encounter Digital Implementation (EDI) system. Sometimes in the middle of an EDI session, you want to run a command but you...
    Posted to Digital Implementation (Weblog) by Kari on Wed, Sep 15 2010
  • What is the syntax for creating pins withing SKILL

    I tried accessing the documentation, but it seems to be unavailable at my university this year. I was just wondering what the syntax for creating a pin is. I think it is dbCreatePin( ) but i don't know the parameters. Also is there a way to specify what material/metal the pin is created on?
    Posted to Custom IC Design (Forum) by JMCaJHU on Wed, Sep 16 2009
  • Input power of a subcircuit

    Hi, I'm simulating with an envlp + pss simulation a rectifier and I would like to estimate the power that goes in input to a subcircuit that implements it. The input voltage of the subcircuit is constant and the current is given by a constant plus an alternating contribution. I tried the following...
    Posted to Custom IC Design (Forum) by Ueue on Mon, Apr 6 2009
  • Re: OCEAN simulation used for envlp analysis

    Thanks for your answer! The version of icfb is 5.1.0, the sub-version 5.10.41.500.5.96! If I generate the netlist in an OCEAN script, in the file input.scs there is not the clockname, as shown in the following lines: " envlp envlp harms=1 stop=200u errpreset=conservative readic="enc.fc"...
    Posted to Custom IC Design (Forum) by Ueue on Fri, Apr 3 2009
  • OCEAN simulation used for envlp analysis

    Hi, I have a problem executing envlp analysis through OCEAN scripts. If I try to execute the simulation with the graphic interface, all is ok, but saving the script and executing it, an error stops the envlp simulation. The error is: " Error found by spectre during envelope following analysis `envlp'...
    Posted to Custom IC Design (Forum) by Ueue on Thu, Apr 2 2009
  • Tech Tip: Viewing The Combined Help for IES-XL

    IES-XL is comprised of IUS, Incisive Verification Kits with Methodology, Specman, and Enterprise Manager in Desktop Mode. One of very common query from Incisive Simulator users is the need to view the help of all the IES-XL components together, in a same help browser. The good news is that it is very...
    Posted to Functional Verification (Weblog) by adua on Fri, Feb 20 2009
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