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functional verification

A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”

By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer at Maxim Integrated, will be happy to see this...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 13 2013
Mode Support for SimVision “Stop Simulation” Button

Prior to Incisive Enterprise Simulator (IES) 12.1, clicking the SimVision "Stop Simulation" button would stop the simulation both in an HDL context and in a Specman context if Specman was present in the simulation. To provide better flexibility in the exact place where you want to pause, the...

Posted to Functional Verification (Weblog) by teamspecman on Wed, May 8 2013
Develop For Debugability – Part II

Looking at Coding Styles for Debug In this blog post we are going to discuss 3 different cases where coding style can help you debug easier: 1. Declarative vs. Sequential Coding 2. Method Call Depth 3. Calculating if-else Conditions Declarative vs. Sequential Coding When modeling your testbench you will...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 23 2013
Multi-Language ml_uvm for e_sv

Hi, for Initial Stage I just create Dummy Wrapper in UVM-SV for Checking purpose... Below is my Dummy file test.sv This file contain - sequence_item,driver,monitor,environement,top_tb,dut and interface... *** => important things are in Bold letter... `include "uvm_macros.svh" interface dut_if;...

Posted to Functional Verification (Forum) by Selvavinayak on Tue, Apr 9 2013
Develop for Debugability – Part 1

Debugging is the most time-critical activity of any verification engineer. Finding a bug is very often a combination of having a good hunch, experience, and the quality of testbench code that you need to analyze. Since having a good hunch and experience is something everyone needs to acquire for themselves...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Apr 8 2013
Slow simulation caused by Assertions

I am using -profile to investigate why my simulation is so slow, and I found the warning: ncsim: *W,FLSTRT the explanation of it is: The assertion is spending a significant amount of time starting new attempts that immediately terminate. In most assertions, such activity can be minimized by optimizations...

Posted to Functional Verification (Forum) by nwang on Thu, Apr 4 2013
Inserting electrical to real connect modules automatically

This is based on the article in EE times http://www.eetimes.com/design/eda-design/4229801/Assertion-based-verification-in-mixed-signal-design vy 2 Cadence authors. Another post similar to this used a VAMS test bench it seems http://www.cadence.com/community/forums/T/22576.aspx . I am trying to implement...

Posted to Mixed-Signal Design (Forum) by abdulahadk on Wed, Mar 27 2013
Creating e Wrapper for system verilog code

Hi all, I am try to creating eRM Wrapper for sv Environment. In that environment systemverilog tasks/function which is called from specman e methods. I have better knowledge in both Verification component. but i need how to interfere this both Verification component. if any body have an Idea about this...

Posted to Functional Verification (Forum) by Selvavinayak on Wed, Mar 27 2013
Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification

Why is there a need for "best practices" in mixed-signal SoC verification, and what are some of those practices? A presentation at the recent DVCon 2013 conference addressed these questions by showing how Maxim Integrated is bringing digital techniques into mixed-signal verification. Here's...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 27 2013
Specman: Getting Source Information on Macros

When you write a define-as or define-as-computed e macro, you sometimes need the replacement code to contain or to depend on the source information regarding the specific macro call, including the source module and the source line number. For example, a macro may need to print source information, or...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Mar 12 2013

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functional verification

A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”

Mode Support for SimVision “Stop Simulation” Button

Develop For Debugability – Part II

Multi-Language ml_uvm for e_sv

Develop for Debugability – Part 1

Slow simulation caused by Assertions

Inserting electrical to real connect modules automatically

Creating e Wrapper for system verilog code

Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification

Specman: Getting Source Information on Macros