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functional verification,SoC

Archived Webinar: SuperSpeed USB 3.0, Verification Challenges, and Solutions

The growing adoption of SuperSpeed USB (USB 3.0) is enabling some exciting new product designs, but it's also causing a big functional verification challenge. A recently archived Cadence webinar provides an overview of the USB 3.0 protocol, notes IC verification requirements and challenges, and shows...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 27 2013
CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification

A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given at CDNLive! Silicon Valley (March 12-13), CDNLive! EMEA (May 6-8), CDNLive! Taiwan (July 11), CDNLive...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 9 2013
Webinar Report: Speeding RTL and Gate-Level Simulation

Every verification team wants faster functional verification performance. Fortunately, there are many ways to achieve that. A recently archived Cadence webinar illustrates a number of techniques for speeding both RTL and gate-level simulation, including "out of the box" improvements to the...

Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 13 2012
EE Times Webinar: Verifying ARM ACE Cache-Coherent Interconnects with UVM

Cache-coherent interconnect is a key component of any SoC that uses the ARM AMBA 4 Coherency Extension ( ACE ) specification. It's hard to design and even harder to verify. A recently archived EE Times webinar shows why cache-coherent interconnect is so complex, and explains how to build a Universal...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 5 2012
The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos. Interface UVC Environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Sep 4 2012
Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Ernie & Duracell "I feel great" - long pause - "I feel great, I feel great". 6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great". I hear this sound coming out of my son's room. What is going on in my house? Is there such a...

Posted to Functional Verification (Weblog) by Axel Scherer on Wed, Aug 1 2012
Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese

A little over two and a half months ago we started sounding the "cowbell" with the release of the UVM SystemVerilog Basics videos . The resonance has been strong. As there can (almost) never be too much of a good thing, we are expanding this series by re-releasing the videos audio dubbed into...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, Jul 23 2012
UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action

Just after releasing the original cowbell video series I found that Ben and Jerry's had discovered a great way to combine cowbells and charity. In April of this year, they held an event for a new world record of over 1600 cowbells in action . It is a must see for the cowbell aficionado. Coincidentally...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, Jul 16 2012
My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e (IEEE 1647)

Growing up on VHDL, moving on to Verilog and then to SystemVerilog, I eventually discovered e (IEEE 1647) Initially I thought: "What is the fuss all about?" While exploring the language during the development of the cowbell videos , it hit me -- I started to recognize the power of Aspect Oriented...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Jul 10 2012
Inefficiency is Futile – Gain UVM e and SystemVerilog Verification Productivity Using Save, Restore, and Reseed

In the world of Star Trek " resistance is futile " when you encounter the Borg . Fortunately, in verification we do not have to deal with the Borg. Nonetheless, our world provides plenty of challenges. Schedules are tight, problems are complex, and market windows are narrow. In other words...

Posted to Functional Verification (Weblog) by Axel Scherer on Fri, Jun 1 2012

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functional verification,SoC

Archived Webinar: SuperSpeed USB 3.0, Verification Challenges, and Solutions

CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification

Webinar Report: Speeding RTL and Gate-Level Simulation

EE Times Webinar: Verifying ARM ACE Cache-Coherent Interconnects with UVM

The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese

UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action

My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e (IEEE 1647)

Inefficiency is Futile – Gain UVM e and SystemVerilog Verification Productivity Using Save, Restore, and Reseed