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functional verification,CDV

Get Started on UVM-e with Free Introductory Video Tutorials

One of the many requests that we get from Specman/ e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM- e basic tutorials . Check them out. These e -based videos are targeted for design and verification engineers...

Posted to Functional Verification (Weblog) by teamspecman on Thu, May 24 2012
The Role of Coverage in Formal Verification, Part 2 Continued…

Recall that three main questions need to be answered to attain coverage in formal verification: Part 1 of this series addressed, "How good are my formal constraints?" In Part 2 we showed debugging of over-constraining with help of examples, addressing the question, "How good is my verification...

Posted to Functional Verification (Weblog) by TeamVerify on Thu, Jan 27 2011
Video: Distinguished Engineer Alok Jain on Formal and Assertion-Based Verification (ABV), Today and Tomorrow

Kicking off 2011, my colleague Alok Jain -- a Distinguished Engineer at Cadence who directs the company's R&D efforts in formal verification -- spoke with Industry Insights columnist Richard Goering . In a wide ranging interview they discussed formal verification usage trends, benefits, roadblocks...

Posted to Functional Verification (Weblog) by jvh3 on Sun, Jan 23 2011
The Role of Coverage in Formal Verification, Part 1 of 3

As outlined in a prior post , new advances in formal and multi-engine technology (like Incisive Enterprise Verifier or "IEV") enables users to do complete verification of design IP using only assertions (i.e. no testbench required!) -- especially for blocks of around 1 million flops or less...

Posted to Functional Verification (Weblog) by TeamVerify on Mon, Jan 3 2011
UVM - 10 Years in the Making ...

In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM). This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology. While there has been...

Posted to Functional Verification (Weblog) by mstellfox on Mon, May 17 2010
When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog?

In my last post I wrote some packet generation code to validate the claim that e code can be up to 3 times more compact vs. the equivalent functionality in SystemVerilog. The result was actually an e description that was more than 3x less than the SystemVerilog equivalent. In this post, let’s see...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 6 2010
DVCon 2010 - Day 2

Click here or on the image below to go to the annotated photo blog of DVCon Day 2. Photos & notes include highlights from: Brett Lammers' paper on "Apples to Apples HVL Comparison Finally Arrives" Lunch panel on "OVM found the bugs, now how do we debug them faster" Cadence...

Posted to Functional Verification (Weblog) by jvh3 on Fri, Feb 26 2010
Yikes - Synopsys is Following Me!

No, I'm not being paranoid -- Synopsys, my largest competitor, is literally following me: Before discoursing on this unusually public display of affection, allow me to take a step back and announce that I've started to tweet on Twitter . While initially put off by the apparent solipsism embedded...

Posted to Functional Verification (Weblog) by jvh3 on Mon, Jun 29 2009
DVCon '09 SaaS Panel Thoughts, Part 1

[Preface / Disclaimer: I haven't yet had the pleasure of working closely with Cadence's own Hosted Design Solutions team, so the following will likely reveal ignorance of strategies and solutions that they already have in place to address the issues outlined below. However, given the ideas this...

Posted to Functional Verification (Weblog) by jvh3 on Wed, Mar 11 2009
Adaptive Chips Selects OVM Over VMM -- An Interview With Amjad Qureshi

On February 11 Cadence announced that Adaptive Chips had adopted the Incisive verification solution using the OVM to improve its verification process. I had the opportunity to "virtually" sit down with Amjad Qureshi, Vice President of Technology at Adaptive Chips, to ask him a few questions...

Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Feb 18 2009

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functional verification,CDV

Get Started on UVM-e with Free Introductory Video Tutorials

The Role of Coverage in Formal Verification, Part 2 Continued…

Video: Distinguished Engineer Alok Jain on Formal and Assertion-Based Verification (ABV), Today and Tomorrow

The Role of Coverage in Formal Verification, Part 1 of 3

UVM - 10 Years in the Making ...

When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog?

DVCon 2010 - Day 2

Yikes - Synopsys is Following Me!

DVCon '09 SaaS Panel Thoughts, Part 1

Adaptive Chips Selects OVM Over VMM -- An Interview With Amjad Qureshi