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formal,Industry Insights,formal verification,DVcon

  • User Experience: Optimizing Power and Area With Formal Verification

    Formal verification can be a powerful tool for low-power design optimization, according to a paper authored by Cadence and Freescale and presented at the recent DVCon conference. The paper showed how formal property checking can validate whether retention flip-flops are controllable, and identify those...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 17 2011
  • At DVCon 2011 Next Week

    Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you with technical papers, panels, and techtorials covering the full range of functional, assertion-based, mixed-signal, and transaction-level verification topics. If you are within a tank of gas or a Southwest flight of San...
    Posted to Functional Verification (Weblog) by jvh3 on Fri, Feb 25 2011
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