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forcing VHDL signal from verilog test

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  • Forcing a VHDL signal from a Verilog Test/Env

    I have a Testbench with a DUT which has VHDL and Verilog RTL modules. The tb_top is verilog. The test file is a verilog. From the verilog test, I need to force a signal inside the DUT several hierarchies down. The signal I need to force is inside a VHDL module. This signal is not available at the top...
    Posted to Functional Verification (Forum) by ashfaqh on Thu, Jul 21 2011
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