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fall time

  • Need help on forward body biasing and CSAFF&CHLFF circuit

    Hi fellow members! i need help on the topic of forward body biasing. I am currently using the 65nm process with a wp/wn ratio of 240/120 which is 2. In regards to the body of the pmos and nmos, i normally tie them to VDD and GND respectively. However, coming upon the topic of forward body biasing i am...
    Posted to Logic Design (Forum) by ntus on Tue, Dec 11 2012
  • Glitch(Spike) in the output..

    Hello..I am new to cadence, I was trying to simulate the simple 'd' latch using cadence, but i noticed that there is a spike in the output going above my supply voltage and below the ground level( i have rise and fall time of clock and D input as 5 ns). When i increase the rise time and fall...
    Posted to Custom IC Design (Forum) by Raki87 on Sun, Oct 28 2012
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