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  • Parasitic extraction of standalone metal traces (IC6.1.5)

    Hi, I have a layout view with multiple metal traces adjacent to one another that I want to simulate as an array of resistors/capacitors. Is there a way to obtain the exact resistance/capacitance of these metal traces through parasitic extraction? I'm assuming there has to be some sort of linking...
    Posted to Custom IC Design (Forum) by Wes8 on Mon, Jan 6 2014
  • Reverse Netlist creation question

    So I am attempting to do something here that I have never done in Cadence. I have tried various approaches throughout the day and have gotten no where. Env: cadence IC514 (not my choice), using PVS DRC/LVS Objective: I was asked to resurrect an old design and import it into a new project env. The design...
    Posted to Custom IC Design (Forum) by srftech on Wed, Sep 5 2012
  • Re: Spectre simulation of calibre extracted layout

    Hi, I know my problem now. it is what Andrew suggested. my circuit had several operating point. My suggestion is that you run DC analysis first to see if both schematic and post-layout simulation results match. if not, you can compare the netllist to find out the difference. sometimes, the schematic...
    Posted to Custom IC Design (Forum) by whlinfei on Fri, Sep 16 2011
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