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  • VIRTUOSO GXL Auto-Place & Route problems

    Hi, I am using the student version of cadence tools at my Univ to auto place and route a custom design, using standard-cells. I am using the Custom IC tools suggested, i.e Schematic XL and Virtuoso GXL. I design the schematic of the architecture, first, then using the connectivity driven option, i generate...
    Posted to Custom IC Design (Forum) by nbtarun on Sat, Apr 3 2010
  • Antenna Error in Calibre DRC but Passed antenna check in Encounter

    Dear Experts, I am using encounter to do my place and route after having obtain the macro lef from the abstract generator, everything's going fine until i stream out my gds2 file and check the DRC using Calibre in virtuoso, where i am getting hundreds of antenna error out of the antenna check. I...
    Posted to Digital Implementation (Forum) by mingfatty on Tue, Mar 16 2010
  • vdd not sensed in post-layout simulation

    Hi, I tried to do post layout simulation with extracted, symbolized inverter, however, I got the message during simualtion: Notice from spectre during topology check. Only one connection to node 'vdd!' I plot the output and confirmed that vdd is not applied to the internal transistors of the...
    Posted to Custom IC Design (Forum) by Malolo on Tue, Jan 12 2010
  • ADE L | post-layout simulation | input.scs error | missing model

    Hi, after successful RLC extraction I got a av_extracted view, which I set in ADE Setup->Environment... in the Switch View List in order to perform post-layout simulation. The netlist is created without any error. However, when I start to run a transient simulation I get te following error: <<...
    Posted to Custom IC Design (Forum) by pitter on Sat, Nov 7 2009
  • Ocean Script error--branch distance too far from generated code

    I met a very wired question these days related to a error: branch distance too far from generated code . Attached please find my ocean script. I will try to discribe the problem in detail, hope some super guys such as Andrew Beckett and skillUser see it and give me some hints. In the attached script...
    Posted to Custom IC Design (Forum) by lunren on Thu, Oct 1 2009
  • ocean -nograph error

    I am very new to ocean plateform and cadence tool. In my simulation, konsole screen display takes most of the time and I want to disable it. I found that "ocean -nograph" does the same. I am trying to use -nograph option but its not work. I don't get any log or output file. Could you please...
    Posted to Custom IC Design (Forum) by nigam214 on Tue, Jul 21 2009
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