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  • Re: [Help]Issues regarding Extraction

    Hi Andrew, Thanks for your advice,Still I have some doubts... Tool version: cadence IC614,ASSURA410,MMSIM 101 I am using two scripts to invoke tool,in that certain variables are used to set lib paths.After invoking tool,Library viewer shows paths are valid and in that analogLib mapped into IC614.But...
    Posted to RF Design (Forum) by hsps on Tue, Sep 10 2013
  • [Help]Issues regarding Extraction

    Hi Friends, I'm facing some issues while doing Extraction including inductances,like ERROR: Failed to find a cellview for (pinductor) ERROR: Failed to find a cellview for (pmind) ERROR: Failed to find a cellview for (vsource) ERROR: Failed to find a cellview for (ccvs) But its working properly for...
    Posted to RF Design (Forum) by hsps on Tue, Sep 10 2013
  • (IC6.1.5.500.12) ADE L messing up sim results(result access). Anyone familiar with that?

    Dear All, I've done extensive searching on forum for this, in vain. However, I am sure that someone else came across this, and maybe my search keywords weren't appropriate. If you know of thread relating to this, please point me to it. From time to time I get the those symptoms (they might all...
    Posted to RF Design (Forum) by ChrisXB on Fri, Jul 19 2013

    Background: I am a complete novice to PCB design with almost no knowledge in this field so please excuse my ignorance, but the task is relatively simple: make a board that changes from one type of connector to another (CHAMP-68 pin to DB37). Basically two pins from the CHAMP-68 converge into one pin...
    Posted to PCB Design (Forum) by joshuad on Thu, Apr 25 2013
  • Analog Design Enviroment Error

    I'm trying a new tecnology and I havent done anything different. Nevertheless, it's giving trouble. I'm receiving this error message, if you know what could be the source of it kindly anwser this post! Error found by spectre during circuit read-in. ERROR (SFE-874): "input.scs" 29...
    Posted to Custom IC Design (Forum) by althoff on Sun, Apr 7 2013
  • OrCAD capture Netlisting error

    Hi, Just wondering if anyone can help me out. I'm trying to simulate a schematic into PSpice but I keep gettting this message: Creating PSpice Netlist INFO(ORNET-1041): Writing PSpice Flat Netlist .\ Cannot remove file .\ ERROR Unable to create netlist file. Any Idea what this might be. I have a...
    Posted to Feedback, Suggestions, and Questions (Forum) by Lulaz on Tue, Mar 26 2013
  • Re: OrCAD Capture 16.3 hangs on load

    Hello, I fell and was also needed for the same situation. However, your reply was seen and the problem was solved. I only exported and performed the contents of registry from another personal computer with which OrCAD16.3 operates normally. Thank you.
    Posted to PCB Design (Forum) by Ponjovi on Fri, Dec 28 2012
  • Error on NC drill (by layer) output file

    Hello, I am designing a 4 layer board with some blind/buried vias. So on “Manufacture -> NC -> NC Drill” I selected under “Drilling” the option “By layer”. There are then generated 3 output files “file-1-2-np.drl”, “file-2-3-np.drl”and...
    Posted to PCB Design (Forum) by Jesus Vasquez on Fri, Dec 7 2012
  • Does anyone ever meet this error in your simulation?

    Hi all, My transition simulation is from 0 to 2us, but a error occurs in the 1.5 us as "spectre - 7031 SST2 error invalid control value". Anyone can help? Thanks a lot~~~
    Posted to RF Design (Forum) by Henrytqy on Thu, Nov 15 2012
  • Layout to PCB Editor library translate error

    Hi When attempting to translate a catalog of library symbols in a max file to a brd file, i get this message on many parts: WARNING ERROR(SPMHDB-204): All SHAPE outline segments must have equal width. Can't create shape/polygon. iges id 890. Continuing. Allegro iges id 890 is the Layout Obstacle...
    Posted to PCB Design (Forum) by bweicher on Wed, Oct 17 2012
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