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error,cadence

  • ERROR DURING SIMULATION

    Sir, First of all, let me thank u for helping me in my project work, by giving valuble information. We are using BSIM-CMG (DG-MOSFET) model for circuit analyses and earlier, we were getting the output waveforms as well as pss analysis results by using virtuoso 6.1.4 version. But last day, the version...
    Posted to RF Design (Forum) by aravindkvarier on Tue, Mar 4 2014
  • Unable to run PSS Analysis

    Sir, I have used BSIM-CMG107.0.0 Mosfet Compact model for my thesis work. But when I go for pss analysis, an error is shown saying that the behavioural file that you have given is not supported for pss analysis. The model is actually a verilog-A file. It would be grateful if you give me any solution...
    Posted to RF Design (Forum) by aravindkvarier on Tue, Feb 11 2014
  • STM065 536 Design Kit

    Hi, I am new with Cadence community I hope I get some help. I start to work on the STM065 536 design kit which support RFCMOS as well. I have a problems with the suitable model libraries that I should load in the ADE env in order to simulate some simple circuit, that for example has PMOS and NMOS of...
    Posted to RF Design (Forum) by paderborn on Fri, Jan 10 2014
  • (IC6.1.5.500.12) ADE L messing up sim results(result access). Anyone familiar with that?

    Dear All, I've done extensive searching on forum for this, in vain. However, I am sure that someone else came across this, and maybe my search keywords weren't appropriate. If you know of thread relating to this, please point me to it. From time to time I get the those symptoms (they might all...
    Posted to RF Design (Forum) by ChrisXB on Fri, Jul 19 2013
  • Multiple Model Files

    Hi, I am working on a circuit where I need multiple model files. The first one I am using is gpdk045, I tried modifying this file to use with transistors from the analog library. The problem I have is that my simulations are wrong whenever I use a transistor with the second model file it just produces...
    Posted to Custom IC Design (Forum) by Karo on Wed, Jul 21 2010
  • VIRTUOSO GXL Auto-Place & Route problems

    Hi, I am using the student version of cadence tools at my Univ to auto place and route a custom design, using standard-cells. I am using the Custom IC tools suggested, i.e Schematic XL and Virtuoso GXL. I design the schematic of the architecture, first, then using the connectivity driven option, i generate...
    Posted to Custom IC Design (Forum) by nbtarun on Sat, Apr 3 2010
  • vdd not sensed in post-layout simulation

    Hi, I tried to do post layout simulation with extracted, symbolized inverter, however, I got the message during simualtion: Notice from spectre during topology check. Only one connection to node 'vdd!' I plot the output and confirmed that vdd is not applied to the internal transistors of the...
    Posted to Custom IC Design (Forum) by Malolo on Tue, Jan 12 2010
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