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  • Synthsis of VHDL-2008 on RC

    Dear All, I developed a design based on VHDL-2008 standard, I can compile it and simulate it pretty fine using NClaunch and SimVision, respectivly. However, I am not able to synthesis the same code using RC. I am using Cadence 5 flow with RC v10.1. What is your recommendations to overcome this issue...
    Posted to Digital Implementation (Forum) by shahein on Thu, Jul 26 2012
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