Home > Community > Tags > encounter/cadence

	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

encounter,cadence

Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment

3D-IC technology has gone from the "grandiose plans" of several years ago to the "practical issues" of ramping up for widespread deployment, according to one panelist at the Electronic Design Process Symposium (EDPS) April 18, 2013 in Monterey, California. That's a pretty good...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 23 2013
Place and route on SOC encounter

Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...

Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
Via Placement issue.

Hi every one, I'm Lakshmi Prashanth, and i'm new to this encounter tool, I've got a problem., initially when i was moving the PG net over the Macros, tool was automatically placing the via's, But suddenly yesterday, some via's are deleted automatically, I don't know how, and If...

Posted to Digital Implementation (Forum) by Leader on Tue, Feb 12 2013
10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions

10nm and 14nm FinFET design will have a lot of challenges, but collaboration among semiconductor ecosystem partners is finding solutions, according to a presentation given at the Common Platform Technology Forum Feb. 5, 2013. The presentation was given by Vassilios Gerousis (right), distinguished engineer...

Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 12 2013
Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

A recent test chip tapeout using the Samsung 14nm FinFET process revealed significant progress in digital implementation at this new process node. Thanks to deep collaboration and extensive R&D investments in libraries, process, and tools, the digital implementation of the test chip was successfully...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 7 2013
Video, Presentation – Low Power Design with ARM Physical and Processor IP

Most system-on-chip designers have two things in common - use of ARM physical and/or processor IP, and a mandate to reduce power consumption. There's a wealth of information on low-power design with ARM IP in a newly available video, as well as presentation slides, from an hour-long presentation...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 17 2012
Mixed Signal Technology Summit Proceedings Now Available

In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees...

Posted to Mixed-Signal Design (Weblog) by nizic on Thu, Dec 13 2012
Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via Technologies about strategies they employed to overcome...

Posted to Logic Design (Weblog) by Kenneth Chang on Tue, Nov 27 2012
ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip

All 20nm test chips are learning experiences, and a recent tapeout of a 20nm Cortex-M0 test chip by ARM engineers was no exception. Completed in June 2012, the test chip design used a Cadence digital implementation flow. The story of the test chip is told in a new guest partner blog (I'm the "guest"...

Posted to Industry Insights (Weblog) by rgoering on Tue, Nov 27 2012
ARM TechCon: Inside Story of a 14nm FinFET Tapeout

The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 31 2012

Page 1 of 3 (26 items) 1 2 3 Next >

Popular Tags

Email

Share

Subscribe

Contact Us

encounter,cadence

Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment

Place and route on SOC encounter

Via Placement issue.

10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions

Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

Video, Presentation – Low Power Design with ARM Physical and Processor IP

Mixed Signal Technology Summit Proceedings Now Available

Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose

ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip

ARM TechCon: Inside Story of a 14nm FinFET Tapeout