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encounter,Incisive

  • Mixed-signal and Low-power Demo -- Cadence Booth at DAC

    0 0 1 556 3170 Cadence Design Systems, Inc. 26 7 3719 14.0 Normal 0 false false false EN-US JA X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-parent...
    Posted to Low Power (Weblog) by QiWang on Fri, May 31 2013
  • Place and route on SOC encounter

    Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
  • Via Placement issue.

    Hi every one, I'm Lakshmi Prashanth, and i'm new to this encounter tool, I've got a problem., initially when i was moving the PG net over the Macros, tool was automatically placing the via's, But suddenly yesterday, some via's are deleted automatically, I don't know how, and If...
    Posted to Digital Implementation (Forum) by Leader on Tue, Feb 12 2013
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
  • EDA Outlook 2010: A Cost-Driven Market

    The worst recession of modern times may be over, but the changes it is leaving in its wake will persist. For surviving semiconductor and systems companies, a new top priority has emerged – controlling and reducing both design costs (implementation and verification) and chip costs (such as die size...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 4 2010
  • Panel Question: Should Designers Do Their Own Verification?

    One question that prompted a lively discussion at the recent Cadence Mixed-Signal Design Summit was whether design engineers should do their own verification. This is a particularly good question for analog and mixed-signal design, where the tradition of separate verification teams is not as strong as...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 11 2009
  • Jurassic Park IV: The Return of ANALOG

    In the lab, no one can hear you scream! When I was getting my BSEE in the 1980s and studying analog and communications, my friends would say, “Why are you studying that old dinosaur, digital is where it’s at!”. Well, far from being consigned to the La Brea tar pit, analog is once again...
    Posted to Custom IC Design (Weblog) by NewYorkSteve on Tue, May 5 2009
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