Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> emulation
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
Verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
emulation
Accelerated Verification IP
Acceleration
accelerator
Accellera
AMD
ARM
AVIP
Bring-up
Broadcom
Cadence
CDNLive
CDNLive!
coverage
DAC
DAC 2011
DAC 2012
DAC breakfast
debug
debugging
Design Automation Conference
DVCon
dynamic power analysis
e language
EDA360
EDA360 Theater
embedded software
Embedded World
emulator
ESL
ESL Market
FPGA
FPGA Based Prototyping
FPGA prototyping
FPGA-based prototypes
FPGA-based prototyping
Freescale
functional verification
Hardware/software co-verification
hardware/software integration
High-level Synthesis
IBM
Imperas
In-circuit acceleration
in-circuit emulation
Incisive
Industry Insights
Intel
LeCroy
low power
low power optimization
LSI
Methods2Business
NextOp
Nufront
Palladium
Palladium XP
Panel
Power
power management
prototypes
Prototyping
Qualcomm
rapid prototyping
Rapid Prototyping Platform
Rohde & Schwarz
RPP
Samsung
SCE-MI
Schirrmeister
Simulation
software
Software Development and Debug
System Design and Verification
System Design and Verification
System Development Suite
system integration
system level
System Realization
SystemC
system-level
system-level design
TLM
transaction
transaction-based
transaction-based acceleration
uvm
verification
Verification Acceleration
Verification Computing Platform
verification IP
VIP
virtual platforms
virtual prototype
virtual prototypes
virtual prototyping
Virtual System Platform
VSP
webinar
Xilinx
Zynq
DAC 2013: User Perspectives on System-Level Verification
The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design Automation Conference ( DAC 2013 ) Tuesday, June...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 15 2013
System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet
Ever since switching from being a hardware/software chip developer to being an enabler with tools in EDA and embedded software, I was part of a team working towards methodologies and tools to improve the interaction of hardware and software. In December last year -- 15 years in -- I summarized a great...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Fri, Mar 8 2013
Securing Invisible Things … or “Why Denial Works!”
The opening keynote of the Embedded World conference in Germany left me with chills. No, it was not a grand theatrical performance letting me crave for more. It simply scared the bejevies out of me with respect to the safety and security of embedded devices, some of which I use each day. Luckily -- as...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Wed, Feb 27 2013
Embedded World 2013: Virtual Platforms Connected to Everything
Sometimes it is hard to explain why certain ideas take off and why others don’t. There are many stories of poor products that are more successful than much better products. There are also many stories about products that struggle in one time or place, but the same thing is a big hit at another...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Fri, Feb 22 2013
System Design 2012 – Real Users Achieving Real Results!
This morning the final success story my team has been working on for this year went live. Texas Instruments reports on how they achieved greater than 90% accurate correlation between an architectural power estimation and actual silicon! This deserves its own blog early next year, but meanwhile, it has...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Fri, Dec 21 2012
Optimizing ARM Based Designs for Low Power using Emulation
The month November goes to the Brits, no question. Not only did the James Bond movie Skyfall open, but Santa Clara also experienced somewhat of a "British Invasion" for ARM TechCon in the Santa Clara convention center. To be there properly I even brought out my favorite new pin striped suit...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Mon, Nov 19 2012
Bill Beausoleil, 1950s Computer Pioneer, Shapes RTL Emulation Technology Today
An important aspect of any advanced technology -- including the RTL emulation systems used for IC verification - is the expertise that stands behind it. Few can claim more expertise than Bill Beausoleil, an IBM, IEEE and Cadence fellow who designed some of the world's first silicon-based computer...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Nov 15 2012
How Many Cycles are Needed to Verify ARM’s big.LITTLE on Palladium XP?
At the recent CDNLive! India user conference, Deepak Venkatesan and Murtaza Johar representing ARM India gave a fascinating presentation called "Verifying big.LITTLE using the Palladium XP". Registered Cadence.com users can get the presentation here once the proceedings are published. ARM's...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Tue, Oct 30 2012
Panelists: Low Power Design Needs System-Level Boost
When low-power design experts get together, much of the conversation turns to the system level. At least that was the case at the recent Low Power Technology Summit held at Cadence Oct. 18, 2012, where audience members questioned panelists about early power estimation, power modeling, and the role of...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Oct 28 2012
Changing the Game with Processor Based Emulation
I have always been fascinated by game changing moves. Some are more successful than others, but the general principle is always the same - coming with a gun to a knife fight. Two of my favorites are from sports. When I was a young rower, the moving outrigger was a game changer for a while and was a fascinating...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Thu, Oct 11 2012
Page 1 of 5 (47 items) 1
2
3
4
5
Next >