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eVC,e

  • Specman Tutorial

    Hi everybody , Can anybody please suggest me quickstart tutorial to specman-e . I have knowledge of systemverilog uvm and now i want to shift to specman e. I Have specman 9.2 and above... are there any tutorials provided by cadence with the tools??? Thanks and regs, Pravin
    Posted to Functional Verification (Forum) by pravintavagad on Mon, Sep 17 2012
  • Error : Overflow, divider cannot be zero

    Hi All, I am using a vr ahb (eVC) and i get this error "Overflow, divider cannot be zero" . I have no clue how to debug this error. Coud anyone please throw some light on thsi error?
    Posted to Functional Verification (Forum) by bharathwajan on Wed, Jun 20 2012
  • event on combination of VHDL and verilog RTL path

    Hi All, I am making one event like : event collect_cover_done_e is rise('~/ve_top_tb_sn.DUT.ve_core_inst.pss_top_inst.pss_ring_inst.pss_core_inst.pss_arcss_core_inst.ipss_dma.done_w')@sim; Here the issue i am getting is : *** Error: From NCVHDL adapter: Missing access rights. No read/write access...
    Posted to Functional Verification (Forum) by Ravisinha on Wed, Dec 1 2010
  • WARN_GLITCH

    Hi All, I am running my e-environment with VHDL testbench and NCSim... while compiling everything is fine.. Till elaboration phase i am not seeing any issue. As soon as i am doing the "run" command in simulator window specman is crashing because of FATAL error (segmentation violation). If i...
    Posted to Functional Verification (Forum) by Ravisinha on Thu, Oct 28 2010
  • end-of-test

    Hi All, I am running one testcase in which i am waiting for power-on-reset to be over and then doing some sequence. In the pre_body i have raised objection and in post_body i have dropped the objection. ISSUE : In the testcase as soon as reset is getting over in the next clock edge i am getting this...
    Posted to Functional Verification (Forum) by Ravisinha on Tue, Oct 19 2010
  • canit able to connect the ports

    Hi all, I have an OVC OVC_A which has a sigmap signal sig_p : list of bit. i need to use this OVC to create other OVC OVC_B which has three diffrent signal consider sig_a ,sig_b ,sig_c. In OVC_A the signal is binded as external. so i extended the sigmap and made as empty. and i tried to connect the OVC_A...
    Posted to Functional Verification (Forum) by specmane on Fri, Feb 12 2010
  • test to write and read registers with field order like packing.low

    Hi, Please, tell me how to test registers when the filed order of a register is packing.low, from a low bit position to a high bit position. I applied the following code by referencing the document 'The Register and Memorr Model', but I could not get correct result. extend MY_REG vr_ad_reg_file...
    Posted to Functional Verification (Forum) by mkyang on Thu, Aug 27 2009
  • The OVM extended to support e and SystemC

    In case you missed the press release, the Open Verification Methodology (OVM) has been updated to support e as well as SystemC: http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=022309_extended_ovm The first implementation of OVM was for SystemVerilog back in 2007. This donation...
    Posted to Functional Verification (Forum) by mstellfox on Wed, Feb 25 2009
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