	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email
Social Web

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

eRM

UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!

A significant number of readers of my previous post on this topic were not aware of the Saturday Night Live cowbell skit. This took me quite by surprise! The only prescription for this problem is that I pledge to continue to play the cultural ambassador and will introduce more vital trivia! However,...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, May 21 2012
UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

To quote an American pop culture catchphrase made famous by Saturday Night Live character Bruce Dickison , "I gotta have more cowbell !" In the world of functional verification this translates to "more collateral!" Thererfore, we have released a set of byte-size videos about the basics...

Posted to Functional Verification (Weblog) by Axel Scherer on Thu, May 3 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 24 2012
Analyzing Error Reports When Specman Crashes

One of the most frustrating events while running a tool would be to experience a tool crash. In Specman you would usually see something like: *** Error: OS signal 11 (segmentation violation) received See the stack trace in ./specman.err To debug: --------- o Rerun the same test with the same seed in...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 17 2012
Non HTML coverage report generation using E-manager

Hi, After my specman regression is complete, I am trying to generate a non-html coverage report using E-manager. When i explored the E-manager tool, I could only see HTML report generation options. Is it not possible to generate non-html reports? or atleast any work around to generate one from html?...

Posted to Functional Verification (Forum) by bharathwajan on Sun, Feb 19 2012
Technical Tip on How to Use HDL Assertions in e

While assertion callbacks have existed in Specman/e for several years now, several questions on their usage have surfaced recently, so here is a short refresher on their usage. ABV (Assertion Based Verification) is, more and more, becoming an important aspect of any complete verification. HDL assertions...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 28 2011
Webinar Seeks to “End the Debate” – e or SystemVerilog?

Which language is best for functional IC verification - e or SystemVerilog? A newly archived Cadence webinar attempts to answer this question by analyzing the key capabilities in both languages, and presenting code comparisons that show how the same functionality would be expressed in either language...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 21 2011
Video: Update on AMIQ’s DVT IDE at DAC 2011 – Specman Debugger Integration, Open API

Specmaniacs and IES-XL users around the world know that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting e RM, OVM, and now the full production UVM. At DAC 2011, AMIQ introduced a long awaited feature to DVT for Specmaniacs in particular...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Jun 22 2011
Is e Old? Yes. Is it Outdated? Definitely Not!

I was at the Design Automation Conference (DAC) last week showcasing our latest, greatest Incisive Enterprise Simulator (IES) performance features in the demo suites. In my "off" time, I was in our DAC booth meeting customers and discussing our advanced verification solutions. I ran into a...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Jun 16 2011
Video: Update on AMIQ’s DVT IDE and UVM 1.0 at DVCon 2011

The UVM 1.0 release was the big story of DVCon 2011, as it's the first verification methodology officially supported by all three of the "Big 3" simulation vendors. However, the very nature of the standard -- an open source library governed by a community similar in character to Linux itself...

Posted to Functional Verification (Weblog) by jvh3 on Wed, Apr 6 2011

Page 1 of 6 (57 items) 1 2 3 4 5 Next > ... Last »

Popular Tags

Share

Subscribe

Contact Us

eRM

UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!

UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Analyzing Error Reports When Specman Crashes

Non HTML coverage report generation using E-manager

Technical Tip on How to Use HDL Assertions in e

Webinar Seeks to “End the Debate” – e or SystemVerilog?

Video: Update on AMIQ’s DVT IDE at DAC 2011 – Specman Debugger Integration, Open API

Is e Old? Yes. Is it Outdated? Definitely Not!

Video: Update on AMIQ’s DVT IDE and UVM 1.0 at DVCon 2011