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eRM,OVM e,OVM ML,OVM

  • UVM - 10 Years in the Making ...

    In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM). This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology. While there has been...
    Posted to Functional Verification (Weblog) by mstellfox on Mon, May 17 2010
  • Cadence Exec: Why Cadence is Comitted to e/Specman

    In case you or your management are wondering about Cadence's commitment to supporting the e language and/or Specman technology, allow us to direct your attention to this interview of Cadence Verification VP Mitch Weaver (who never worked for Verisity, BTW) by industry analyst Richard Goering. As...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Feb 16 2010
  • DVCon 2010 For The Specmaniac

    At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies ( full list of Cadence-sponsored activities is posted here ). Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language...
    Posted to Functional Verification (Weblog) by teamspecman on Mon, Feb 15 2010
  • OVM Innovation Means Business

    Today, Cadence recognized it's OVM team for their innovative contribution to the Cadence enterprise starting in 2008. Why enterprise? To me, enterprise is the most exciting part because it underscore how the OVM has rallied all of Cadence verification around a common cause which has both polished...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Nov 3 2009
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