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e

  • EDA Standards Review and Forecast, Part 1 – Accellera and IEEE

    Given increasing design complexity and skyrocketing costs, EDA standards have never been more important. As noted in the EDA360 vision paper , a standards-based ecosystem is absolutely essential if we're going to design the hardware and software that's needed to support tomorrow's creative...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 20 2010
  • event on combination of VHDL and verilog RTL path

    Hi All, I am making one event like : event collect_cover_done_e is rise('~/ve_top_tb_sn.DUT.ve_core_inst.pss_top_inst.pss_ring_inst.pss_core_inst.pss_arcss_core_inst.ipss_dma.done_w')@sim; Here the issue i am getting is : *** Error: From NCVHDL adapter: Missing access rights. No read/write access...
    Posted to Functional Verification (Forum) by Ravisinha on Wed, Dec 1 2010
  • 2010 CDNLive Silicon Valley Photo Blog: Silicon Realization, ABV, OVM, MDV, Specman, Formal and More

    If you are running short on time and can't view all the videos of the 2010 CDNLive Silicon Valley in San Jose, CA on October 26 posted here: www.cadence.com/cdnlive/na/2010/pages/default.aspx consider this photo blog as your very own "Cliff Notes" version. Click here to go to the gallery...
    Posted to Functional Verification (Weblog) by jvh3 on Tue, Nov 9 2010
  • WARN_GLITCH

    Hi All, I am running my e-environment with VHDL testbench and NCSim... while compiling everything is fine.. Till elaboration phase i am not seeing any issue. As soon as i am doing the "run" command in simulator window specman is crashing because of FATAL error (segmentation violation). If i...
    Posted to Functional Verification (Forum) by Ravisinha on Thu, Oct 28 2010
  • e Templates and e Macros -- An Update for Specman Users

    A couple of recent blogs have mentioned the feature of e templates, which was added to Specman relatively recently. If you are used to e macros -- the feature that has existed in the e language almost since forever -- you may wonder if it's not just the same concept in a different form. In other...
    Posted to Functional Verification (Weblog) by teamspecman on Fri, Oct 22 2010
  • end-of-test

    Hi All, I am running one testcase in which i am waiting for power-on-reset to be over and then doing some sequence. In the pre_body i have raised objection and in post_body i have dropped the objection. ISSUE : In the testcase as soon as reset is getting over in the next clock edge i am getting this...
    Posted to Functional Verification (Forum) by Ravisinha on Tue, Oct 19 2010
  • e Templates and Aspect Oriented Programming

    In a recent blog - " e Templates: A Nifty Way To Create Reusable Code ", Corey Goss wrote about the useful feature of template types, which lets you write reusable code. In this post I'll show how the combination of templates and aspect-oriented programming (AOP) allows you to make such...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Sep 21 2010
  • User Interview: Verifying IP With Many Configurations

    As manager of hardware development for the Graphics Competence Center at Fujitsu Semiconductor Europe , Raimund Soenning faces some tough challenges. He's responsible for the design and verification of complex graphics controller SoCs for automotive applications. His group develops graphics and video...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 1 2010
  • vr_ad_file multiple instance

    Hello All, I have a situation where i want to implement 8 instance of some particular reg_file which all have many reg_def and reg_fld. For example : I have 8 instance of one DUT module (TEST0, TEST1,TEST2... TEST8), since its all are the instance so all the instance will have the sets of registers....
    Posted to Functional Verification (Forum) by Ravisinha on Wed, Sep 1 2010
  • vr_ad_reg_file multiple instance

    Hello All, I have a situation where i want to implement 8 instance of some particular reg_file which all have many reg_def and reg_fld. For example : I have 8 instance of one DUT module (TEST0, TEST1,TEST2... TEST8), since its all are the instance so all the instance will have the sets of registers....
    Posted to Functional Verification Shared Code (Forum) by Ravisinha on Mon, Aug 30 2010
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