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  • help with reflection

    Hi all I am looking for a way to get all the local variables within a specific method. i didn't find an API function in rf_method struct that do such operation. i will happy if some one can show me how it is done. Regards. EM
    Posted to Functional Verification (Forum) by myonlyscreen on Thu, Mar 21 2013
  • DVCon 2013: Functional Verification Is EDA’s “Killer App”

    With another year of record attendance, DVCon has again proven that a functional verification-focused mix of trade show and technical conference is what customers need to get their jobs done. Here are some of the some of the highlights I took away from this informative event: DVCon 2013 was a one stop...
    Posted to Functional Verification (Weblog) by jvh3 on Sun, Mar 10 2013
  • Bidirectional has() and count() List Pseudo-Methods

    Hi. As of the 11.1 release, the list.has() and list.count() list pseudo-methods can be treated as bidirectional constraint operators. In 11.1, list.has() and list.count() are solved unidirectionally by default. To ensure that these pseudo-methods are solved as bidirectional expressions, set the config...
    Posted to Functional Verification (Forum) by IonutC on Tue, Mar 5 2013
  • DVCon 2013 for the Specmaniac

    At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here ). Of course, Team Specman cannot resist drawing your attention to the many activities that will feature Specman and...
    Posted to Functional Verification (Weblog) by teamspecman on Thu, Feb 7 2013
  • UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

    Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 11 2012
  • Re: time between two events

    you have sys.time and sys.realtime. You can log the time value when an event happens (using for example and on block) and next time you can calculate the delta. -hannes
    Posted to Functional Verification (Forum) by hannes on Thu, Oct 11 2012
  • Re: Specman Tutorial

    Hi Pravin. Welcome to the Specman world! I'm sure you will like it here ;-) If you crank up the "cdnshelp" tool and look under the "Incisive Verification Kits" topic you will find a wealth of self-paced tutorials / workshops to experiment with. These guide you through constructing...
    Posted to Functional Verification (Forum) by StephenH on Mon, Sep 17 2012
  • Specman Tutorial

    Hi everybody , Can anybody please suggest me quickstart tutorial to specman-e . I have knowledge of systemverilog uvm and now i want to shift to specman e. I Have specman 9.2 and above... are there any tutorials provided by cadence with the tools??? Thanks and regs, Pravin
    Posted to Functional Verification (Forum) by pravintavagad on Mon, Sep 17 2012
  • Re: RE: Verification Plan using Eplanner

    Hello Mahi. Please note that set_cover_check() has nothing to do with disabling checks, it only controls the coverage of the checks. Assuming that you want to disable the coverage of the checks but keep the checks active for error checking, then set_cover_check() is the right method to use. However I'm...
    Posted to Functional Verification (Forum) by StephenH on Tue, Aug 14 2012
  • Re: vr_ad register definition utility

    Hi Thoufiq. We (Cadence) are making improvements to vr_ad at the moment so it's a good time to make feature requests, but can I please ask you to do so via the official support system (i.e. contact a Cadence AE directly or file a support ticket at http://support.cadence.com). The reason for this...
    Posted to Functional Verification Shared Code (Forum) by StephenH on Fri, Aug 3 2012
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