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e,NCSim,VHDL Signal Verilog Module

  • WARN_GLITCH

    Hi All, I am running my e-environment with VHDL testbench and NCSim... while compiling everything is fine.. Till elaboration phase i am not seeing any issue. As soon as i am doing the "run" command in simulator window specman is crashing because of FATAL error (segmentation violation). If i...
    Posted to Functional Verification (Forum) by Ravisinha on Thu, Oct 28 2010
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