Home > Community > Tags > e/IES/IEEE 1647/Testbench simulation
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

e,IES,IEEE 1647,Testbench simulation

  • Get Started on UVM-e with Free Introductory Video Tutorials

    One of the many requests that we get from Specman/ e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM- e basic tutorials . Check them out. These e -based videos are targeted for design and verification engineers...
    Posted to Functional Verification (Weblog) by teamspecman on Thu, May 24 2012
  • e Templates: A Nifty Way To Create Reusable Code

    Hi All, An e template (known as a parameterized type in other programming languages) is a feature that has been around for several releases and can be a great way of creating re-usable code. Templates can be used anywhere a user would like to create a single re-useable object that might operate on different...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Aug 10 2010
  • "ClubT" Newsletter Issue #3 Just Posted

    Specmaniacs and Other Trailblazers, The latest edition of the 'ClubT ' newsletter is now posted here , and once again there is exciting news around e , Specman, and Verification. Articles include: * Have you heard of OVM e ? * Incisive 8.2 Technology Update * Verification IP Portfolio E-x-p-a...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Jan 27 2009
  • Using e Ports

    The other day I saw some posts to the Yahoo Specman group regarding e ports. The last one in the thread asked for some introductory information on ports which I thought might make a good topic for my entry today. As I was researching what I wanted to include in the post when I came across some related...
    Posted to Functional Verification (Weblog) by teamspecman on Fri, Dec 19 2008
  • Constraint Layering - Fine Tuning Your Environment - Part 2

    In my last post , I talked briefly about constraint layering in which I gave an extremely simple example of how users can layer constraints on an existing base environment to change how that base environment behaves, all without touching the base environment. Obviously, we all know that our verification...
    Posted to Functional Verification (Weblog) by teamspecman on Fri, Dec 12 2008
  • New e / Specman Workshops Available Now

    In response to the continual growth in the e /Specman user community, Team Specman has put together 3 new workshops that are included with the Incisive 8.2 SOCV Kit that shipped just last week. (Plus: to ensure the content stays fresh, the "plan of record" for these workshops is to continually...
    Posted to Functional Verification (Weblog) by teamspecman on Wed, Dec 10 2008
  • New Blog - All About e & Specman

    End-users of e , Specman, Incisive Enterprise Simulator (IES), e RM/OVM e , and loyal Specmaniacs in general: have we got the blog for you! As part of Cadence's commitment to support IEEE 1647 e , Team Specman is launching this blog to serve up technical tips, tricks, examples, and observations about...
    Posted to Functional Verification (Weblog) by teamspecman on Wed, Dec 10 2008
  • e Running Inside VCS Anniversary Updates?

    It's been a year since I heard the first solid report about Synopsys supporting the e language (IEEE 1647-2008) natively inside VCS. (Note a key distinction here: VCS has interfaced with e language and/or Specman-driven testbenches for years -- that's not what I'm referring to. The issue...
    Posted to Functional Verification (Weblog) by jvh3 on Thu, Nov 20 2008
Page 1 of 1 (8 items)