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double patterning,design rules
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TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies
The TSMC 2013 Technology Symposium , held April 9 in San Jose, California, brought good news for anyone interested in advanced node or 3D-IC technologies. Keynote speakers noted excellent yields and significant progress in 20nm planar, 16nm FinFET, and Chip-on-Wafer-on-Substrate (CoWoS) technologies...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 14 2013
Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation
A recent test chip tapeout using the Samsung 14nm FinFET process revealed significant progress in digital implementation at this new process node. Thanks to deep collaboration and extensive R&D investments in libraries, process, and tools, the digital implementation of the test chip was successfully...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 7 2013
Whitepaper: New Methodology Needed for 20nm Custom/Analog IC Design
Before digital SoC designers take advantage of the power, performance and density advantages of 20nm, custom/analog designers must develop the standard cells and the analog/mixed-signal IP. Thus, no 20nm solution is complete without an integrated custom/analog capability. A newly published Cadence whitepaper...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Nov 13 2012
Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges
Any discussion about advanced node (below 28nm) that focuses only on digital design is missing an important part of the story. Custom/analog design must be considered too, and that's the subject of a video interview with Tom Beckley, senior vice president of R&D for Custom IC and Simulation at...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 5 2012
ARM TechCon: Design at 14nm (or 10nm) – What’s Going to Change
The next semiconductor process node after 20nm promises tremendous power and performance benefits, but also poses some new challenges, according to a presentation by ARM and IBM at the ARM TechCon conference Oct. 30, 2012. The presentation showed how the "second generation" of double patterning...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Fri, Nov 2 2012
ARM TechCon: Inside Story of a 14nm FinFET Tapeout
The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 31 2012
Q&A: TSMC R&D VP Cliff Hou Discusses 20nm, CoWoS Multi-Die Packaging, and FinFETs
T he recent TSMC Open Innovation Platform (OIP) 2012 Ecosystem Forum marked the release of 20nm and chip-on-wafer-on-substrate (CoWoS) reference flows, as well as new insights about the giant foundry's plan for 16nm FinFETs. I blogged about the keynote speeches here . Separately, I interviewed one...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 24 2012
Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements
No 20nm IC design "solution" is complete without a custom/analog flow that can develop standard cells and analog/mixed-signal IP blocks. That custom/analog flow requires some changes to keep up with 20nm challenges such as double patterning and layout-dependent effects (LDE). A good overview...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 9 2012
On-Line Presentation: 20nm Design Challenges, and a Look Ahead to 14nm
The Common Platform Technology Forum held March 14 in Santa Clara, California, provided an updated look at process technology, design challenges, and ecosystem collaboration at 28nm and below. Much of the content is available throughout 2012 as part of a Virtual Technology Forum . Following is a report...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 19 2012
Q&A: A Look at 20nm Design Challenges and Solutions
The 20nm process node promises tremendous advantages in power, performance and design capacity, but also raises tough design challenges. These challenges include increased timing and power variability, complex layout rules, and incredibly large designs with massive amounts of IP. A major new challenge...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Sep 11 2011
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