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double patterning

  • DAC Panel: 20nm is Tough, But Not a Roadblock
    So far the move to lower semiconductor process nodes has continued unabated, but the upcoming 20nm node is causing a lot of concern. Lithography is so challenging that extra masks ( double patterning ) will be required. Will designs be technically and economically feasible? Panelists at the Design Automation...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 6 2011

  • Common Platform Forum: A Clearer Path to Advanced Process Nodes
    Insights into what you can expect at 32/28nm and below came to the forefront at the Common Platform Technology Forum Jan. 18, a well-attended one-day event in Silicon Valley. One point that caught my attention is that IBM is turning to a "gate last" high-k metal gate (HKMG) technology at 20nm...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Jan 18 2011

  • ARM Techcon: IBM Speaker Outlines Path to 22nm and Beyond
    An IBM industry address at this week's ARM Technology Conference ( ARM Techcon ) included both inspiration and a warning. The inspiration came from optimistic descriptions of the technologies that will propel us to 22nm and below. The warning was that it takes at least 10 years to bring new silicon...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 10 2010

  • Double Patterning – A Double Edged Sword?
    Double patterning lithography, which splits designs into two or more masks, will probably be required at 22 nm and below. The plus side is that it will extend current optical lithography equipment to yet another process generation. But it will also add some costs, require new EDA tool capabilities, and...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 3 2009
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